DATE
2006
IEEE
14 years 5 months ago
2006
IEEE
The impact of test conditions on the detectability of open defects is investigated. We performed an inductive fault analysis on representative standard gates. The simulation resul...
DATE
2006
IEEE
14 years 5 months ago
2006
IEEE
DATE
2006
IEEE
14 years 5 months ago
2006
IEEE
—In this paper we describe a methodology to measure exactly the quality of fault-tolerant designs by combining faultinjection in high level design (HLD) descriptions with a forma...
DATE
2006
IEEE
14 years 5 months ago
2006
IEEE
Today’s nanometer technology trends have a very negative impact on the reliability of semiconductor products. Intermittent faults constitute the largest part of reliability fail...
DATE
2006
IEEE
14 years 5 months ago
2006
IEEE
Functional validation is a major bottleneck in pipelined processor design. Simulation using functional test vectors is the most widely used form of processor validation. While exi...
DATE
2006
IEEE
14 years 5 months ago
2006
IEEE
Most of the challenges related to the development of multi-processor platforms for complex wireless and multimedia applications fall into the Electronic System Level (ESL) domain....
DATE
2006
IEEE
14 years 5 months ago
2006
IEEE
In traditional parallel co-simulation approaches, the simulation speed is heavily limited by time synchronization overhead between simulators and idle time caused by data dependen...
DATE
2006
IEEE
14 years 5 months ago
2006
IEEE
DATE
2006
IEEE
14 years 5 months ago
2006
IEEE
DATE
2006
IEEE
14 years 5 months ago
2006
IEEE
High level synthesis transformations play a major part in shaping the properties of the final circuit. However, most optimizations are performed without much knowledge of the fina...