—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
- Parallel architectures have become an increasingly popular method in which to achieve high performance with low power consumption. In order to leverage these benefits, applicatio...
RTOS Simulation Henning Zabel, Wolfgang Mueller Universität Paderborn, C-LAB Fürstenallee 11, D-33102 Paderborn, Germany —Today, mobile and embedded real-time systems have to c...
—Due to increasing complexity of design interactions between the chip, package and PCB, it is essential to consider them at the same time. Specifically the finger/pad locations...
Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu,...
Abstract—Flash memory is a good candidate for the storage device in real-time systems due to its non-fluctuating performance, low power consumption and high shock resistance. Ho...
—Core-cell stability represents the ability of the core-cell to keep the stored data. With the rapid development of semiconductor memories, their test is becoming a major concern...
Alexandre Ney, Luigi Dilillo, Patrick Girard, Serg...
We address the problem of real-time streaming applications scheduling on hybrid CPU/FPGA architectures. The main contribution is a two-step approach to minimize the buffer require...
— In this paper, we present an X-Fill (QC-Fill) method for not only slashing the test time but also reducing the test power (including both capture power and shifting power). QC-...