DATE
2009
IEEE
14 years 6 months ago
2009
IEEE
Multi-domain clock skew scheduling is a cost effective technique for performance improvement. However, the required wire length and area overhead due to phase shifters for realizin...
DATE
2009
IEEE
14 years 6 months ago
2009
IEEE
—With the trend toward high-quality large form factor displays on high-end handhelds, LCD backlight accounts for a significant and increasing percentage of the total energy budg...
DATE
2009
IEEE
14 years 6 months ago
2009
IEEE
Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory a...
DATE
2009
IEEE
14 years 6 months ago
2009
IEEE
- Clock skew scheduling (CSS) is an effective technique to optimize clock period of sequential designs. However, these techniques are not effective in the presence of certain desig...
DATE
2009
IEEE
14 years 6 months ago
2009
IEEE
— Statistical static timing analysis deals with the increasing variations in manufacturing processes to reduce the pessimism in the worst case timing analysis. Because of the cor...
DATE
2009
IEEE
14 years 6 months ago
2009
IEEE
— During volume testing, test application time, test data volume and high performance automatic test equipment (ATE) are the major cost factors. Embedded testing including builti...
DATE
2009
IEEE
14 years 6 months ago
2009
IEEE
Abstract—Chip multiprocessors (CMPs) present a unique scenario for software data prefetching with subtle tradeoffs between memory bandwidth and performance. In a shared L2 based ...
DATE
2009
IEEE
14 years 6 months ago
2009
IEEE
—During post-silicon processor debugging, we need to frequently capture and dump out the internal state of the processor. Since internal state constitutes all memory elements, th...
DATE
2009
IEEE
14 years 6 months ago
2009
IEEE
DATE
2009
IEEE
14 years 6 months ago
2009
IEEE
Abstract—To deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between...