Sciweavers

DAC
2001
ACM
14 years 9 months ago
Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip
We present a design flow for the generation of application-specific multiprocessor architectures. In the flow, architectural parameters are first extracted from a high-level syste...
Damien Lyonnard, Sungjoo Yoo, Amer Baghdadi, Ahmed...
DAC
2001
ACM
14 years 9 months ago
Battery-Aware Static Scheduling for Distributed Real-Time Embedded Systems
This paper addresses battery-aware static scheduling in batterypowered distributed real-time embedded systems. As suggested by previous work, reducing the discharge current level ...
Jiong Luo, Niraj K. Jha
DAC
2001
ACM
14 years 9 months ago
High-Quality Operation Binding for Clustered VLIW Datapaths
Clustering is an effective method to increase the available parallelism in VLIW datapaths without incurring severe penalties associated with large number of register file ports. E...
Viktor S. Lapinskii, Margarida F. Jacome, Gustavo ...
DAC
2001
ACM
14 years 9 months ago
LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs
This paper presents LOTTERYBUS, a novel high-performance communication architecture for system-on-chip (SoC) designs. The LOTTERYBUS architecture was designed to address the follo...
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshmi...
DAC
2001
ACM
14 years 9 months ago
A Framework for Object Oriented Hardware Specification, Verification, and Synthesis
We describe two things. First, we present a uniform framework for object oriented specification and verification of hardware. For this purpose the object oriented language `e'...
Tommy Kuhn, Tobias Oppold, Markus Winterholer, Wol...
DAC
2001
ACM
14 years 9 months ago
Circuit-based Boolean Reasoning
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuit...
Andreas Kuehlmann, Malay K. Ganai, Viresh Paruthi
DAC
2001
ACM
14 years 9 months ago
Automated Pipeline Design
The interlock and forwarding logic is considered the tricky part of a fully-featured pipelined microprocessor and especially debugging these parts delays the hardware design proce...
Daniel Kroening, Wolfgang J. Paul
DAC
2001
ACM
14 years 9 months ago
Detection of Partially Simultaneously Alive Signals in Storage Requirement Estimation for Data Intensive Applications
In this paper, we propose a novel storage requirement estimation methodology for use in the early system design phases when the data transfer ordering is only partially fixed. At ...
Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. ...