Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays. Semiconductor Industry Association (SIA) roadmap predicts that, beyond the ...
Shukri J. Souri, Kaustav Banerjee, Amit Mehrotra, ...
A dynamic noise model is developed and applied to analyze the noise immunity of precharge-evaluate circuits. Considering that the primary source of noise-injection in the circuit ...
In this paper, we present a case study for the design, programming and usage of a reconfigurable system-on-chip, MorphoSys, which is targeted at computation-intensive applications...
Hartej Singh, Guangming Lu, Eliseu M. Chaves Filho...
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
We have developed a function-level power estimation methodology for predicting the power dissipation of embedded software. For a given microprocessor core, we empirically build th...
Gang Qu, Naoyuki Kawabe, Kimiyoshi Usami, Miodrag ...
In this paper, we introduce a new technique for modeling and solving the dynamic power management (DPM) problem for systems with complex behavioral characteristics such as concurr...
This paper presents a D/A converter with a 14-bit intrinsic linearity in 0.5?m CMOS technology, which has been designed using a systematic design methodology for current-steering ...
Geert Van der Plas, Jan Vandenbussche, Walter Daem...