Sciweavers

DFT
2003
IEEE
106views VLSI» more  DFT 2003»
14 years 5 months ago
Techniques for Transient Fault Sensitivity Analysis and Reduction in VLSI Circuits
Transient faults in VLSI circuits could lead to disastrous consequences. With technology scaling, circuits are becoming increasingly vulnerable to transient faults. This papers pr...
Atul Maheshwari, Israel Koren, Wayne Burleson
DFT
2003
IEEE
98views VLSI» more  DFT 2003»
14 years 5 months ago
Constrained ATPG for Broadside Transition Testing
In this paper, we propose a new concept of testing only functionally testable transition faults in Broadside Transition testing via a novel constrained ATPG. For each functionally...
Xiao Liu, Michael S. Hsiao
DFT
2003
IEEE
113views VLSI» more  DFT 2003»
14 years 5 months ago
Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip
Test scheduling and Test Access Mechanism (TAM) design are two important tasks in the development of a System-on-Chip (SOC) test solution. Previous test scheduling techniques assu...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
DFT
2003
IEEE
79views VLSI» more  DFT 2003»
14 years 5 months ago
Hybrid BIST Using an Incrementally Guided LFSR
A new hybrid BIST scheme is proposed which is based on using an “incrementally guided LFSR.” It very efficiently combines external deterministic data from the tester with on-c...
C. V. Krishna, Nur A. Touba
DFT
2003
IEEE
64views VLSI» more  DFT 2003»
14 years 5 months ago
Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture
1 This paper presents a solution to the test time minimization problem for core-based systems that contain sequential cores with STUMPS architecture. We assume a hybrid BIST approa...
Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, ...
DFT
2003
IEEE
132views VLSI» more  DFT 2003»
14 years 5 months ago
Level-Hybrid Optoelectronic TESH Interconnection Network
This paper discusses a hybrid optoelectronic scheme for a new interconnection network, "Tori connected mESHes (TESH)". The major features of TESH are the following: it i...
Vijay K. Jain, Glenn H. Chapman
DFT
2003
IEEE
151views VLSI» more  DFT 2003»
14 years 5 months ago
Soft-Error Detection Using Control Flow Assertions
Over the last years, an increasing number of safety-critical tasks have been demanded to computer systems. In this paper, a software-based approach for developing safety-critical
O. Goloubeva, Maurizio Rebaudengo, Matteo Sonza Re...
DFT
2003
IEEE
83views VLSI» more  DFT 2003»
14 years 5 months ago
Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse Faults
This paper proposes a new fault model and its modeling and analysis methods in a clockless asynchronous wave pipeline for extensive yield evaluation and assurance. It is highly de...
T. Feng, Nohpill Park, Yong-Bin Kim, Vincenzo Piur...
DFT
2003
IEEE
120views VLSI» more  DFT 2003»
14 years 5 months ago
Implementation and Testing of Fault-Tolerant Photodiode-Based Active Pixel Sensor (APS)
The implementation of imaging arrays for System-On-a-Chip (SOC) is aided by using faulttolerant light sensors. Fault-tolerant redundancy in an Active Pixel Sensor (APS) is obtaine...
Sunjaya Djaja, Glenn H. Chapman, Desmond Y. H. Che...
DFT
2003
IEEE
100views VLSI» more  DFT 2003»
14 years 5 months ago
Scan-Based BIST Diagnosis Using an Embedded Processor
For system-on-chip designs that contain an embedded processor, this paper present a software based diagnosis scheme that can make use of the processor to aid in diagnosis in a sca...
Kedarnath J. Balakrishnan, Nur A. Touba