We present a new timing driven method for global placement. Our method is based on the observation that similar net length reductions in the different nets that make up a path may...
In this paper a wave-pipelining scheme is used to increase the performance of a router architecture. Wave-pipelining has a potential of significantly reducing clock cycle time an...
System-level power exploration requires tools for estimation of the overall power consumed by a system, as well as a detailed breakdown of the consumption of its main functional b...
Luca Benini, Marco Ferrero, Alberto Macii, Enrico ...
— Typically, placement algorithms attempt to minimize the total net length of a printed circuit board (PCB). However, an MCM’s increased throughput and dense circuitry can easi...
In many applications such as high-level synthesis (HLS) and logic synthesis and possibly engineering change order (ECO) we would like to get fast and accurate estimations of diffe...