Sciweavers

CODES
2008
IEEE
14 years 6 months ago
You can catch more bugs with transaction level honey
In this special session we explore holistic approaches to hardware/software debug that use or integrate transaction level models (TLMs). We present several TLM-based approaches to...
Miron Abramovici, Kees Goossens, Bart Vermeulen, J...
CODES
2008
IEEE
14 years 6 months ago
SPaC: a symbolic pareto calculator
The compositional computation of Pareto points in multi-dimensional optimization problems is an important means to efficiently explore the optimization space. This paper presents ...
Hamid Shojaei, Twan Basten, Marc Geilen, Phillip S...
CODES
2008
IEEE
14 years 6 months ago
Distributed and low-power synchronization architecture for embedded multiprocessors
In this paper we present a framework for a distributed and very low-cost implementation of synchronization controllers and protocols for embedded multiprocessors. The proposed arc...
Chenjie Yu, Peter Petrov
CODES
2008
IEEE
14 years 6 months ago
Intra- and inter-processor hybrid performance modeling for MPSoC architectures
The heterogeneity of modern MPSoC architectures, coupled with the increasing complexity of the applications mapped onto them has recently led to a lot of interest in hybrid perfor...
Frank E. B. Ophelders, Samarjit Chakraborty, Henk ...
CODES
2009
IEEE
14 years 6 months ago
Using binary translation in event driven simulation for fast and flexible MPSoC simulation
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
Marius Gligor, Nicolas Fournel, Frédé...
CODES
2009
IEEE
14 years 6 months ago
A standby-sparing technique with low energy-overhead for fault-tolerant hard real-time systems
Time redundancy (rollback-recovery) and hardware redundancy are commonly used in real-time systems to achieve fault tolerance. From an energy consumption point of view, time redun...
Alireza Ejlali, Bashir M. Al-Hashimi, Petru Eles
CODES
2009
IEEE
14 years 6 months ago
Exploiting data-redundancy in reliability-aware networked embedded system design
This paper presents a system-level design methodology for networked embedded systems that exploits existing data-redundancy to increase their reliability. The presented approach n...
Martin Lukasiewycz, Michael Glaß, Jürge...
CODES
2009
IEEE
14 years 6 months ago
An on-chip interconnect and protocol stack for multiple communication paradigms and programming models
A growing number of applications, with diverse requirements, are integrated on the same System on Chip (SoC) in the form of hardware and software Intellectual Property (IP). The d...
Andreas Hansson, Kees Goossens
CODES
2009
IEEE
14 years 6 months ago
A variation-tolerant scheduler for better than worst-case behavioral synthesis
– There has been a recent shift in design paradigms, with many turning towards yield-driven approaches to synthesize and design systems. A major cause of this shift is the contin...
Jason Cong, Albert Liu, Bin Liu
CODES
2009
IEEE
14 years 6 months ago
A high-level virtual platform for early MPSoC software development
Multiprocessor System-on-Chips (MPSoCs) are nowadays widely used, but the problem of their software development persists to be one of the biggest challenges for developers. Virtua...
Jianjiang Ceng, Weihua Sheng, Jerónimo Cast...