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DATE
2008
IEEE
121views Hardware» more  DATE 2008»
14 years 3 months ago
A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy
We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy, or more generally, a suboptimality in the synthe...
Irith Pomeranz, Sudhakar M. Reddy
DATE
2008
IEEE
131views Hardware» more  DATE 2008»
14 years 3 months ago
Scheduling of Fault-Tolerant Embedded Systems with Soft and Hard Timing Constraints
In this paper we present an approach to the synthesis of fault-tolerant schedules for embedded applications with soft and hard real-time constraints. We are interested to guarante...
Viacheslav Izosimov, Paul Pop, Petru Eles, Zebo Pe...
DATE
2008
IEEE
138views Hardware» more  DATE 2008»
14 years 3 months ago
BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs
A novel routing algorithm, named Balanced Adaptive Routing Protocol (BARP), is proposed for NoCs to provide adaptive routing and ensure deadlock-free and livelock-free routing at ...
Pejman Lotfi-Kamran, Masoud Daneshtalab, Caro Luca...
DATE
2008
IEEE
217views Hardware» more  DATE 2008»
14 years 3 months ago
A Coarse-Grained Array based Baseband Processor for 100Mbps+ Software Defined Radio
The Software-Defined Radio (SDR) concept aims to enabling costeffective multi-mode baseband solutions for wireless terminals. However, the growing complexity of new communication ...
Bruno Bougard, Bjorn De Sutter, Sebastien Rabou, D...
DATE
2008
IEEE
79views Hardware» more  DATE 2008»
14 years 3 months ago
An efficient algorithm for free resources management on the FPGA
Yi Lu 0004, Thomas Marconi, Georgi Gaydadjiev, Koe...
DATE
2008
IEEE
121views Hardware» more  DATE 2008»
14 years 3 months ago
A Generic Standard Cell Design Methodology for Differential Circuit Styles
In this paper we present a generic methodology for the rapid generation and implementation of standard cell libraries for differential circuit design styles. We demonstrate a syst...
Stéphane Badel, Erdem Guleyupoglu, Ozgur In...
DATE
2008
IEEE
114views Hardware» more  DATE 2008»
14 years 3 months ago
Operating System Controlled Processor-Memory Bus Encryption
—Unencrypted data appearing on the processor– memory bus can result in security violations, e.g., allowing attackers to gather keys to financial accounts and personal data. Al...
Xi Chen, Robert P. Dick, Alok N. Choudhary