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DATE
2008
IEEE
123views Hardware» more  DATE 2008»
14 years 3 months ago
Verification of Temporal Properties in Automotive Embedded Software
Djones Lettnin, Pradeep Kumar Nalla, Jürgen R...
DATE
2008
IEEE
121views Hardware» more  DATE 2008»
14 years 3 months ago
On Automated Trigger Event Generation in Post-Silicon Validation
When searching for functional bugs in silicon, debug data is acquired after a trigger event occurs. A trigger event can be configured at run-time using a set of control registers...
Ho Fai Ko, Nicola Nicolici
DATE
2008
IEEE
114views Hardware» more  DATE 2008»
14 years 3 months ago
Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
Sanghyun Park, Aviral Shrivastava, Yunheung Paek
DATE
2008
IEEE
120views Hardware» more  DATE 2008»
14 years 3 months ago
Error Detection/Correction in DNA Algorithmic Self-Assembly
A novel error detection/correction technique for algorithmic self-assembly is presented in this paper. Through the use of a tile set that allows errors to be isolated and propagat...
Stephen Frechette, Fabrizio Lombardi
DATE
2008
IEEE
226views Hardware» more  DATE 2008»
14 years 3 months ago
A General Method to Evaluate RF BIST Techniques Based on Non-parametric Density Estimation
Abstract— We present a general method to evaluate RF BuiltIn Self-Test (BIST) techniques during the design stage. In particular, the adaptive kernel estimator is used to construc...
Haralampos-G. D. Stratigopoulos, Jeanne Tongbong, ...
DATE
2008
IEEE
78views Hardware» more  DATE 2008»
14 years 3 months ago
Transistor-Specific Delay Modeling for SSTA
SSTA has received a considerable amount of attention in recent years. However, it is a general rule that any approach can only be as accurate as the underlying models. Thus, varia...
Brian Cline, Kaviraj Chopra, David Blaauw, Andres ...
DATE
2008
IEEE
106views Hardware» more  DATE 2008»
14 years 3 months ago
Modeling Event Stream Hierarchies with Hierarchical Event Models
Compositional Scheduling Analysis couples local scheduling analysis via event streams. While local analysis has successfully been extended to include hierarchical scheduling strat...
Jonas Rox, Rolf Ernst
DATE
2008
IEEE
145views Hardware» more  DATE 2008»
14 years 3 months ago
Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures
We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the route...
Mohammad Abdullah Al Faruque, Jörg Henkel
DATE
2008
IEEE
112views Hardware» more  DATE 2008»
14 years 3 months ago
Tool Support for Incremental Failure Mode and Effects Analysis of Component-Based Systems
Failure Mode and Effects Analysis (FMEA) is a wellknown technique widely used for safety assessment in the area of safety-critical systems. However, FMEA is traditionally done man...
Jonas Elmqvist, Simin Nadjm-Tehrani