Sciweavers

ICCAD
2003
IEEE
111views Hardware» more  ICCAD 2003»
14 years 6 months ago
A Trade-off Oriented Placement Tool
High quality placement results are always produced at the cost of significant runtimes. In this paper, we study the trade-off between the overall quality and the runtime for stand...
Huaiyu Xu, Maogang Wang, Bo-Kyung Choi, Majid Sarr...
ICCAD
2003
IEEE
137views Hardware» more  ICCAD 2003»
14 years 6 months ago
Bus-Driven Floorplanning
In this paper, we present an integrated approach to floorplanning and bus planning, i.e., bus-driven floorplanning (BDF). We are given a set of circuit blocks and the bus speci...
Hua Xiang, Xiaoping Tang, Martin D. F. Wong
ICCAD
2003
IEEE
124views Hardware» more  ICCAD 2003»
14 years 6 months ago
Gradual Relaxation Techniques with Applications to Behavioral Synthesis
Heuristics are widely used for solving computational intractable synthesis problems. However, until now, there has been limited effort to systematically develop heuristics that ca...
Zhiru Zhang, Yiping Fan, Miodrag Potkonjak, Jason ...
ICCAD
2003
IEEE
159views Hardware» more  ICCAD 2003»
14 years 6 months ago
Energy-Aware Fault Tolerance in Fixed-Priority Real-Time Embedded Systems
We investigate an integrated approach to fault tolerance and dynamic power management in real-time embedded systems. Fault tolerance is achieved via checkpointing and power manage...
Ying Zhang, Krishnendu Chakrabarty, Vishnu Swamina...
ICCAD
2003
IEEE
141views Hardware» more  ICCAD 2003»
14 years 6 months ago
Passive Synthesis of Compact Frequency-Dependent Interconnect Models via Quadrature Spectral Rules
In this paper, we present a reduced order inodeling methodology, based on the utilization of optimal non-uniform grids generated by Gaussian spectral rules, for the direct passive...
Traianos Yioultsis, Anne Woo, Andreas C. Cangellar...
ICCAD
2003
IEEE
138views Hardware» more  ICCAD 2003»
14 years 6 months ago
Multi-Million Gate FPGA Physical Design Challenges
The recent past has seen a tremendous increase in the size of design circuits that can be implemented in a single FPGA. These large design sizes significantly impact cycle time du...
Maogang Wang, Abhishek Ranjan, Salil Raje
ICCAD
2003
IEEE
120views Hardware» more  ICCAD 2003»
14 years 6 months ago
RTL Power Optimization with Gate-Level Accuracy
Traditional RTL power optimization techniques commit transformations at the RTL based on the estimation of area, delay and power. However, because of inadequate power and delay in...
Qi Wang, Sumit Roy
ICCAD
2003
IEEE
148views Hardware» more  ICCAD 2003»
14 years 6 months ago
The Compositional Far Side of Image Computation
Symbolic image computation is the most fundamental computation in BDD-based sequential system optimization and formal verification. In this paper, we explore the use of over-appr...
Chao Wang, Gary D. Hachtel, Fabio Somenzi
ICCAD
2003
IEEE
221views Hardware» more  ICCAD 2003»
14 years 6 months ago
Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems
Abstract— Dynamic voltage scaling (DVS) is a powerful technique for reducing dynamic power consumption in a computing system. However, as technology feature size continues to sca...
Le Yan, Jiong Luo, Niraj K. Jha
ICCAD
2003
IEEE
152views Hardware» more  ICCAD 2003»
14 years 6 months ago
Efficient Iterative Time Preconditioners for Harmonic Balance RF Circuit Simulation
Efficient iterative time preconditioners for Krylovbased harmonic balance circuit simulators are proposed. Some numerical experiments assess their performance relative to the well...
Fabrice Veersé