High quality placement results are always produced at the cost of significant runtimes. In this paper, we study the trade-off between the overall quality and the runtime for stand...
In this paper, we present an integrated approach to floorplanning and bus planning, i.e., bus-driven floorplanning (BDF). We are given a set of circuit blocks and the bus speci...
Heuristics are widely used for solving computational intractable synthesis problems. However, until now, there has been limited effort to systematically develop heuristics that ca...
Zhiru Zhang, Yiping Fan, Miodrag Potkonjak, Jason ...
We investigate an integrated approach to fault tolerance and dynamic power management in real-time embedded systems. Fault tolerance is achieved via checkpointing and power manage...
In this paper, we present a reduced order inodeling methodology, based on the utilization of optimal non-uniform grids generated by Gaussian spectral rules, for the direct passive...
Traianos Yioultsis, Anne Woo, Andreas C. Cangellar...
The recent past has seen a tremendous increase in the size of design circuits that can be implemented in a single FPGA. These large design sizes significantly impact cycle time du...
Traditional RTL power optimization techniques commit transformations at the RTL based on the estimation of area, delay and power. However, because of inadequate power and delay in...
Symbolic image computation is the most fundamental computation in BDD-based sequential system optimization and formal verification. In this paper, we explore the use of over-appr...
Abstract— Dynamic voltage scaling (DVS) is a powerful technique for reducing dynamic power consumption in a computing system. However, as technology feature size continues to sca...
Efficient iterative time preconditioners for Krylovbased harmonic balance circuit simulators are proposed. Some numerical experiments assess their performance relative to the well...