—While array structures are a significant source of power dissipation, there is a lack of accurate high-level power estimators that account for varying array circuit implementat...
Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt,...
This paper introduces a CAD framework for co-simulation of hybrid circuits containing CMOS and SET (Single Electron Transistor) devices. An improved analytical model for SET is al...
Transmitting compressed data can reduce inter-processor communication traffic and create new opportunities for DVS (dynamic voltage scaling) in distributed embedded systems. Howe...
Routing for FPGAs has been a very challenging problem due to the limitation of routing resources. Although the FPGA routing problem has been researched extensively, most algorithm...
In this paper, we study the full-chp interconnect power modeling. ,We show that repeater,insertion is no longer sufficient to achievethe targetfrequencies specifiedhy ITRS, and de...
As Field-Programmable Gate Array (FPGA) power consumption continues to increase, lower power FPGA circuitry, architectures, and Computer-Aided Design (CAD) tools need to be develo...
Modeling frequency-dependent nonlinear characteristics of complex analog blocks and subsystems is critical for enabling efficient verification of mixed-signal system designs. Rece...
A high performance communication architecture, SAMBA-bus, is proposed in this paper. In SAMBA-bus, multiple compatible bus transactions can be performed simultaneously with only a...
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming...