ICCAD
2005
IEEE
14 years 10 months ago
2005
IEEE
— One of the critical goals in code optimization for MPSoC architectures is to minimize the number of off-chip memory accesses. This is because such accesses can be extremely cos...
ICCAD
2005
IEEE
14 years 10 months ago
2005
IEEE
In this paper we present NoCEE, a fast and accurate method for extracting energy models for packet-switched Network on Chip (NoC) routers. Linear regression is used to model the r...
ICCAD
2005
IEEE
14 years 10 months ago
2005
IEEE
— When exploring computing elements made from technologies other than CMOS, it is imperative to investigate the effects of physical implementation constraints. This paper focuses...
ICCAD
2005
IEEE
14 years 10 months ago
2005
IEEE
Technology mapping based on DAG-covering suffers from the problem of structural bias: the structure of the mapped netlist depends strongly on the subject graph. In this paper we ...
ICCAD
2005
IEEE
14 years 10 months ago
2005
IEEE
Abstract— We present in this paper a new interconnect-driven multilevel floorplanning, called IMF, to handle large-scale building-module designs. Unlike the traditional multilev...
ICCAD
2005
IEEE
14 years 10 months ago
2005
IEEE
— In this paper we present a parameterized reduction technique for non-linear systems. Our approach combines an existing non-parameterized trajectory piecewise linear method for ...
ICCAD
2006
IEEE
14 years 10 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
ICCAD
2006
IEEE
14 years 10 months ago
2006
IEEE
Ignoring the effect of simultaneous switching for logic gates causes silicon failures for high performance microprocessor designs. The main reason to omit this effect is the run...
ICCAD
2006
IEEE
14 years 10 months ago
2006
IEEE
Because of the increasing dominance of interconnect issues in advanced IC technology, placement has become a critical step in the IC design flow. To get accurate interconnect inf...
ICCAD
2006
IEEE
14 years 10 months ago
2006
IEEE
Statistical static timing analysis (SSTA) is emerging as a solution for predicting the timing characteristics of digital circuits under process variability. For computing the stat...