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ICCAD
2005
IEEE
110views Hardware» more  ICCAD 2005»
14 years 6 months ago
Computational geometry based placement migration
Placement migration is a critical step to address a variety of postplacement design closure issues, such as timing, routing congestion, signal integrity, and heat distribution. To...
Tao Luo, Haoxing Ren, Charles J. Alpert, David Zhi...
ICCAD
2005
IEEE
113views Hardware» more  ICCAD 2005»
14 years 6 months ago
Synthesis methodology for built-in at-speed testing
We discuss a new synthesis flow, which offers the ability to do easy delay testing almost free in terms of its impact on speed and area as compared to corresponding implementation...
Yinghua Li, Alex Kondratyev, Robert K. Brayton
ICCAD
2005
IEEE
98views Hardware» more  ICCAD 2005»
14 years 6 months ago
Clustering for processing rate optimization
Clustering (or partitioning) is a crucial step between logic synthesis and physical design in the layout of a large scale design. A design verified at the logic synthesis level m...
Chuan Lin, Jia Wang, Hai Zhou
ICCAD
2005
IEEE
127views Hardware» more  ICCAD 2005»
14 years 6 months ago
Flip-flop insertion with shifted-phase clocks for FPGA power reduction
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
Hyeonmin Lim, Kyungsoo Lee, Youngjin Cho, Naehyuck...
ICCAD
2005
IEEE
98views Hardware» more  ICCAD 2005»
14 years 6 months ago
Statistical based link insertion for robust clock network design
We present a statistical based non-tree clock distribution construction algorithm that starts with a tree and incrementally insert cross links, such that the skew variation of the...
Wai-Ching Douglas Lam, J. Jam, Cheng-Kok Koh, Venk...
ICCAD
2005
IEEE
101views Hardware» more  ICCAD 2005»
14 years 6 months ago
Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variat
In this paper we propose a novel parameterized interconnect order reduction algorithm, CORE, to efficiently capture both inter-die and intra-die variations. CORE applies a two-ste...
Xin Li, Peng Li, Lawrence T. Pileggi
ICCAD
2005
IEEE
100views Hardware» more  ICCAD 2005»
14 years 6 months ago
Performance-centering optimization for system-level analog design exploration
In this paper we propose a novel analog design optimization methodology to address two key aspects of top-down system-level design: (1) how to optimally compare and select analog ...
Xin Li, Jian Wang, Lawrence T. Pileggi, Tun-Shih C...
ICCAD
2005
IEEE
107views Hardware» more  ICCAD 2005»
14 years 6 months ago
Projection-based performance modeling for inter/intra-die variations
Large-scale process fluctuations in nano-scale IC technologies suggest applying high-order (e.g., quadratic) response surface models to capture the circuit performance variations....
Xin Li, Jiayong Le, Lawrence T. Pileggi, Andrzej J...
ICCAD
2005
IEEE
151views Hardware» more  ICCAD 2005»
14 years 6 months ago
Architecture and details of a high quality, large-scale analytical placer
Modern design requirements have brought additional complexities to netlists and layouts. Millions of components, whitespace resources, and fixed/movable blocks are just a few to ...
Andrew B. Kahng, Sherief Reda, Qinke Wang