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ICCAD
2005
IEEE
122views Hardware» more  ICCAD 2005»
14 years 6 months ago
Intrinsic shortest path length: a new, accurate a priori wirelength estimator
A priori wirelength estimation is concerned with predicting various wirelength characteristics before placement. In this work we propose a novel, accurate estimator of net lengths...
Andrew B. Kahng, Sherief Reda
ICCAD
2005
IEEE
130views Hardware» more  ICCAD 2005»
14 years 6 months ago
A cache-defect-aware code placement algorithm for improving the performance of processors
— Yield improvement through exploiting fault-free sections of defective chips is a well-known technique [1][2]. The idea is to partition the circuitry of a chip in a way that fau...
Tohru Ishihara, Farzan Fallah
ICCAD
2005
IEEE
114views Hardware» more  ICCAD 2005»
14 years 6 months ago
Statistical timing analysis with two-sided constraints
Based on a timing yield model, a statistical static timing analysis technique is proposed. This technique preserves existing methodology by selecting a “device file setting” ...
Khaled R. Heloue, Farid N. Najm
ICCAD
2005
IEEE
133views Hardware» more  ICCAD 2005»
14 years 6 months ago
Gate sizing using incremental parameterized statistical timing analysis
— As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
Matthew R. Guthaus, Natesan Venkateswaran, Chandu ...
ICCAD
2005
IEEE
79views Hardware» more  ICCAD 2005»
14 years 6 months ago
The impact of the nanoscale on computing systems
— Nanoscale technologies provide both challenges and opportunities. We show that the issues and potential solutions facing designers are technology independent and arise mainly f...
Seth Copen Goldstein
ICCAD
2005
IEEE
132views Hardware» more  ICCAD 2005»
14 years 6 months ago
Serial-link bus: a low-power on-chip bus architecture
As technology scales, the shrinking wire width increases the interconnect resistivity, while the decreasing interconnect spacing significantly increases the coupling capacitance. ...
Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khell...
ICCAD
2005
IEEE
112views Hardware» more  ICCAD 2005»
14 years 6 months ago
Global signaling over lossy transmission lines
We describe an interconnect scheme based on lossy transmission lines, compare this scheme with traditional bus based links, and present performance data. Unlike some other schemes...
Michael P. Flynn, Joshua Jaeyoung Kang
ICCAD
2005
IEEE
144views Hardware» more  ICCAD 2005»
14 years 6 months ago
An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications
— In this paper we propose an exact algorithm that maximizes the sharing of partial terms in Multiple Constant Multiplication (MCM) operations. We model this problem as a Boolean...
Paulo F. Flores, José C. Monteiro, Eduardo ...
ICCAD
2005
IEEE
108views Hardware» more  ICCAD 2005»
14 years 6 months ago
A routing algorithm for flip-chip design
— The flip-chip package gives the highest chip density of any packaging method to support the pad-limited Application-Specific Integrated Circuit (ASIC) designs. In this paper,...
Jia-Wei Fang, I-Jye Lin, Ping-Hung Yuh, Yao-Wen Ch...