Sciweavers

ICCD
2003
IEEE
140views Hardware» more  ICCD 2003»
14 years 9 months ago
Cost-Efficient Memory Architecture Design of NAND Flash Memory Embedded Systems
NAND flash memory has become an indispensable component in embedded systems because of its versatile features such as non-volatility, solid-state reliability, low cos,t and high d...
Chanik Park, Jaeyu Seo, Dongyoung Seo, Shinhan Kim...
ICCD
2003
IEEE
105views Hardware» more  ICCD 2003»
14 years 9 months ago
Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling
— We model the power fluctuation as cycle-to-cycle power gradient and minimize the mean of the power gradients using ILP. We propose scheduling schemes for three modes of datapa...
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappi...
ICCD
2003
IEEE
123views Hardware» more  ICCD 2003»
14 years 9 months ago
Simplifying SoC design with the Customizable Control Processor Platform
With the circuit density available in today’s ASIC design systems, increased integration is possible creating more complexity in the design of a System on a Chip (SoC). IBM’s ...
C. Ross Ogilvie, Richard Ray, Robert Devins, Mark ...
ICCD
2003
IEEE
121views Hardware» more  ICCD 2003»
14 years 9 months ago
Interface Synthesis using Memory Mapping for an FPGA Platform
Manev Luthra, Sumit Gupta, Nikil D. Dutt, Rajesh K...
ICCD
2003
IEEE
140views Hardware» more  ICCD 2003»
14 years 9 months ago
Reducing Multimedia Decode Power using Feedback Control
Despite recent advances, battery life continues to be a limiting factor in mobile multimedia systems. Significant energy savings can be achieved by adapting systems at runtime to...
Zhijian Lu, John Lach, Mircea R. Stan, Kevin Skadr...
ICCD
2003
IEEE
147views Hardware» more  ICCD 2003»
14 years 9 months ago
An Efficient VLIW DSP Architecture for Baseband Processing
The VLIW processors with static instruction scheduling and thus deterministic execution times are very suitable for highperformance real-time DSP applications. But the two major w...
Tay-Jyi Lin, Chin-Chi Chang, Chen-Chia Lee, Chein-...
ICCD
2003
IEEE
165views Hardware» more  ICCD 2003»
14 years 9 months ago
CMOS High-Speed I/Os - Present and Future
High-speed I/O circuits, once used only for PHYs, are now widely used for intra-system signaling as well because of their bandwidth, power, area, and cost advantages. This technol...
M.-J. Edward Lee, William J. Dally, Ramin Farjad-R...
ICCD
2003
IEEE
121views Hardware» more  ICCD 2003»
14 years 9 months ago
Distributed Reorder Buffer Schemes for Low Power
We consider several approaches for reducing the complexity and power dissipation in processors that use separate register file to maintain the commited register values. The first ...
Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad ...
ICCD
2003
IEEE
145views Hardware» more  ICCD 2003»
14 years 9 months ago
Care Bit Density and Test Cube Clusters: Multi-Level Compression Opportunities
: Most of the recently discussed and commercially introduced test stimulus data compression techniques are based on low care bit densities found in typical scan test vectors. Data ...
Bernd Könemann