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ICCD
2003
IEEE
130views Hardware» more  ICCD 2003»
14 years 9 months ago
On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume
This paper presents a pinpoint test set relaxation method for test compression that maximally derives the capability of a run-length encoding technique such as Golomb coding or fr...
Seiji Kajihara, Yasumi Doi, Lei Li, Krishnendu Cha...
ICCD
2003
IEEE
147views Hardware» more  ICCD 2003»
14 years 9 months ago
Design Flow Enhancements for DNA Arrays
DNA probe arrays have recently emerged as one of the core genomic technologies. Exploiting analogies between manufacturing processes for DNA arrays and for VLSI chips, we demonstr...
Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu ...
ICCD
2003
IEEE
109views Hardware» more  ICCD 2003»
14 years 9 months ago
Independent Test Sequence Compaction through Integer Programming
We discuss the compaction of independent test sequences for sequential circuits. Our first contribution is the formulation of this problem as an integer program, which we then so...
Petros Drineas, Yiorgos Makris
ICCD
2003
IEEE
83views Hardware» more  ICCD 2003»
14 years 9 months ago
Physical Design of the "2.5D" Stacked System
Yangdong Deng, Wojciech Maly
ICCD
2003
IEEE
129views Hardware» more  ICCD 2003»
14 years 9 months ago
Reducing dTLB Energy Through Dynamic Resizing
Translation Look-aside Buffer (TLB), which is small Content Addressable Memory (CAM) structure used to translate virtual addresses to physical addresses, can consume significant ...
Victor Delaluz, Mahmut T. Kandemir, Anand Sivasubr...
ICCD
2003
IEEE
98views Hardware» more  ICCD 2003»
14 years 9 months ago
Specifying and Verifying Systems with Multiple Clocks
Multiple clock domains are a challenge for hardware specification and verification. We present a method for specifying the relations between multiple clocks, and for modeling th...
Edmund M. Clarke, Daniel Kroening, Karen Yorav
ICCD
2003
IEEE
111views Hardware» more  ICCD 2003»
14 years 9 months ago
Reducing Operand Transport Complexity of Superscalar Processors using Distributed Register Files
A critical problem in wide-issue superscalar processors is the limit on cycle time imposed by the central register file and operand bypass network. In this paper, a distributed re...
Santithorn Bunchua, D. Scott Wills, Linda M. Wills
ICCD
2003
IEEE
143views Hardware» more  ICCD 2003»
14 years 9 months ago
Cost-Effective Graceful Degradation in Speculative Processor Subsystems: The Branch Prediction Case
We analyze the effect of errors in branch predictors, a representative example of speculative processor subsystems, to motivate the necessity for fault tolerance in such subsystem...
Sobeeh Almukhaizim, Thomas Verdel, Yiorgos Makris
ICCD
2003
IEEE
104views Hardware» more  ICCD 2003»
14 years 9 months ago
On Reducing Register Pressure and Energy in Multiple-Banked Register Files
The storage for speculative values in superscalar processors is one of the main sources of complexity and power dissipation. In this paper, we present a novel technique to reduce ...
Jaume Abella, Antonio González
ICCD
2003
IEEE
112views Hardware» more  ICCD 2003»
14 years 9 months ago
Power Efficient Data Cache Designs
This paper investigates some power efficient data cache designs that try to significantly reduce the cache energy consumption, both static and dynamic, with a minimal impact in pe...
Jaume Abella, Antonio González