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ACSD
2001
IEEE
118views Hardware» more  ACSD 2001»
14 years 9 days ago
Correct Performance of Transaction Capabilities
The correctness of an optimisation of the Transport Capabilities Application Part of the Signalling System No. 7 is formalised as a branching bisimulation which is relaxed to allo...
Thomas Arts, Izak van Langevelde
ACSD
2001
IEEE
112views Hardware» more  ACSD 2001»
14 years 9 days ago
Software Implementation of Synchronous Programs
Synchronous languages allow a high level, concurrent, and deterministic description the behavior of reactive systems. Thus, they can be used advantageously for the programming of ...
Charles Andre, Frédéric Boulanger, A...
FPL
2006
Springer
113views Hardware» more  FPL 2006»
14 years 9 days ago
A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design
This paper is concerned with the application of formal optimisation methods to the design of mixed-granularity FPGAs. In particular, we investigate the appropriate mix and floorpl...
Alastair M. Smith, George A. Constantinides, Peter...
FPL
2006
Springer
81views Hardware» more  FPL 2006»
14 years 9 days ago
A Dynamic Reconfigurable Fabric for Platform SoCs
Christos A. Papachristou, J. Weaver, R. Vijayakuma...
FPL
2006
Springer
95views Hardware» more  FPL 2006»
14 years 9 days ago
A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor
This paper presents a reconfigurable functional unit (RFU) for an adaptive dynamic extensible processor. The processor can tune its extended instructions to the target application...
Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, K...
FPL
2006
Springer
119views Hardware» more  FPL 2006»
14 years 9 days ago
The Entropy of FPGA Reconfiguration
In line with Shannon's ideas, we define the entropy of FPGA reconfiguration to be the amount of information needed to configure a given circuit onto a given device. We propos...
Usama Malik, Oliver Diessel
FPL
2006
Springer
211views Hardware» more  FPL 2006»
14 years 9 days ago
Comparing FPGAs to Graphics Accelerators and the Playstation 2 Using a Unified Source Description
Field programmable gate arrays (FPGAs), graphics processing units (GPUs) and Sony's PlayStation 2 vector units offer scope for hardware acceleration of applications. We compa...
Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckm...
FPL
2006
Springer
147views Hardware» more  FPL 2006»
14 years 9 days ago
Secure Content Distribution System Based on Run-Time Partial Hardware Reconfiguration
A secure content distribution system is prototyped based on run-time partial reconfigurability of an FPGA. The system provides a robust content protection scheme for online conten...
Yohei Hori, Hiroyuki Yokoyama, Kenji Toda
FPL
2006
Springer
96views Hardware» more  FPL 2006»
14 years 9 days ago
High Speed Document Clustering in Reconfigurable Hardware
High-performance document clustering systems enable similar documents to automatically self-organize into groups. In the past, the large amount of computational time needed to clu...
G. Adam Covington, Charles L. G. Comstock, Andrew ...