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FPL
2006
Springer
118views Hardware» more  FPL 2006»
14 years 9 days ago
Activity Estimation for Field-Programmable Gate Arrays
This paper examines various activity estimation techniques in order to determine which are most appropriate for use in the context of field-programmable gate arrays (FPGAs). Speci...
Julien Lamoureux, Steven J. E. Wilton
FPL
2006
Springer
147views Hardware» more  FPL 2006»
14 years 9 days ago
Non-Uniform Random Number Generation Through Piecewise Linear Approximations
This paper presents a hardware architecture for non-uniform random number generation, which allows the generator's distribution to be modified at run-time without reconfigura...
David B. Thomas, Wayne Luk
FPL
2006
Springer
95views Hardware» more  FPL 2006»
14 years 9 days ago
Automation of IP Core Interface Generation for Reconfigurable Computing
Pre-designed IP cores for FPGAs represent a huge intellectual and financial wealth that must be leveraged by any high-level tool targeting reconfigurable platforms. In this paper ...
Zhi Guo, Abhishek Mitra, Walid A. Najjar
FPL
2006
Springer
125views Hardware» more  FPL 2006»
14 years 9 days ago
Application-Specific Memory Interleaving for FPGA-Based Grid Computations: A General Design Technique
Many compute-intensive applications generate single result values by accessing clusters of nearby points in grids of one, two, or more dimensions. Often, the performance of FGPA i...
Tom Van Court, Martin C. Herbordt
FPL
2006
Springer
98views Hardware» more  FPL 2006»
14 years 9 days ago
Self-Reconfigurable Pervasive Platform for Cryptographic Application
The complexity exhibited by pervasive systems is constantly increasing. Customer electronics devices provide day to day a larger amount of functionalities. A common approach for g...
Arnaud Lagger, Andres Upegui, Eduardo Sanchez, Iva...
FPL
2006
Springer
124views Hardware» more  FPL 2006»
14 years 9 days ago
A Dynamically Reconfigurable Queue Scheduler
In this paper we present the design and implementation of a dynamically reconfigurable system for packet queue scheduling. Two widely accepted queue schedulers have been implement...
Christoforos Kachris, Stamatis Vassiliadis
FPL
2006
Springer
96views Hardware» more  FPL 2006»
14 years 9 days ago
Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding
Interconnect delays are becoming an increasingly significant part of the critical path delay for circuits implemented in FPGAs. Pipelined interconnects have been proposed to addre...
Allan Carroll, Carl Ebeling
FPL
2006
Springer
91views Hardware» more  FPL 2006»
14 years 9 days ago
Multi-Bit Carry Chains for High-Performance Reconfigurable Fabrics
Ripple-carry architectures are the norm in today's reconfigurable fabrics. They are simple, require minimal routing, and are easily formed across arbitrary cells in a fabric....
Michael T. Frederick, Arun K. Somani
FPL
2006
Springer
123views Hardware» more  FPL 2006»
14 years 9 days ago
Improved Interpolation and System Integration for FPGA-Based Molecular Dynamics Simulations
: FPGA-based acceleration of molecular dynamics (MD) has been the subject of several recent studies. Here we describe a new non-bonded force computation pipeline implemented on a 2...
Yongfeng Gu, Tom Van Court, Martin C. Herbordt
FPL
2006
Springer
137views Hardware» more  FPL 2006»
14 years 9 days ago
FPGA Performance Optimization Via Chipwise Placement Considering Process Variations
Both custom IC and FPGA designs in the nanometer regime suffer from process variations. But different from custom ICs, FPGAs' programmability offers a unique design freedom t...
Lerong Cheng, Jinjun Xiong, Lei He, Mike Hutton