Sciweavers

DATE
2004
IEEE
127views Hardware» more  DATE 2004»
14 years 12 days ago
Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA
M. Bellato, Paolo Bernardi, D. Bortolato, A. Cande...
DATE
2004
IEEE
120views Hardware» more  DATE 2004»
14 years 12 days ago
Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study
In this paper we describe how we applied a BIST-based approach to the test of a logic core to be included in System-on-achip (SoC) environments. The approach advantages are the ab...
Paolo Bernardi, Guido Masera, Federico Quaglio, Ma...
DATE
2004
IEEE
138views Hardware» more  DATE 2004»
14 years 12 days ago
Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors
This paper proposes a low-energy solution for CAMbased highly associative I-caches using a segmented wordline and a predictor-based instruction fetch mechanism. Not all instructio...
Juan L. Aragón, Dan Nicolaescu, Alexander V...
DATE
2004
IEEE
128views Hardware» more  DATE 2004»
14 years 12 days ago
Enhanced Diameter Bounding via Structural
Bounded model checking (BMC) has gained widespread industrial use due to its relative scalability. Its exhaustiveness over all valid input vectors allows it to expose arbitrarily ...
Jason Baumgartner, Andreas Kuehlmann
DATE
2004
IEEE
185views Hardware» more  DATE 2004»
14 years 12 days ago
Energy-Aware System Design for Wireless Multimedia
In this paper, we present various challenges that arise in the delivery and exchange of multimedia information to mobile devices. Specifically, we focus on techniques for maintain...
Hans Van Antwerpen, Nikil D. Dutt, Rajesh K. Gupta...
DATE
2004
IEEE
123views Hardware» more  DATE 2004»
14 years 12 days ago
On Concurrent Error Detection with Bounded Latency in FSMs
We discuss the problem of concurrent error detection (CED) with bounded latency in finite state machines (FSMs). The objective of this approach is to reduce the overhead of CED, a...
Sobeeh Almukhaizim, Petros Drineas, Yiorgos Makris
DATE
2004
IEEE
108views Hardware» more  DATE 2004»
14 years 12 days ago
Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures
Nikhil Bansal, Sumit Gupta, Nikil Dutt, Alexandru ...
DATE
2004
IEEE
114views Hardware» more  DATE 2004»
14 years 12 days ago
Synthesis of Reversible Logic
Abhinav Agrawal, Niraj K. Jha
DATE
2004
IEEE
129views Hardware» more  DATE 2004»
14 years 12 days ago
Improving Design and Verification Productivity with VHDL-200x
Stephen Bailey, Erich Marschner, Jayaram Bhasker, ...
DATE
2004
IEEE
113views Hardware» more  DATE 2004»
14 years 12 days ago
Dynamic Memory Management Design Methodology for Reduced Memory Footprint in Multimedia and Wireless Network Applications
New portable consumer embedded devices must execute multimedia and wireless network applications that demand extensive memory footprint. Moreover, they must heavily rely on Dynami...
David Atienza, Stylianos Mamagkakis, Francky Catth...