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DATE
2004
IEEE
139views Hardware» more  DATE 2004»
14 years 12 days ago
From Synchronous to Asynchronous: An Automatic Approach
This paper presents a methodology to derive asynchronous circuits from optimized synchronous circuits by replacing the clock distribution tree by a handshaking network. A case stu...
Jordi Cortadella, Alex Kondratyev, Luciano Lavagno...
DATE
2004
IEEE
116views Hardware» more  DATE 2004»
14 years 12 days ago
OCCN: A Network-On-Chip Modeling and Simulation Framework
Marcello Coppola, Stephane Curaba, Miltos D. Gramm...
DATE
2004
IEEE
136views Hardware» more  DATE 2004»
14 years 12 days ago
An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems
Recently a lot of multimedia applications are emerging on portable appliances. They require both the flexibility of upgradeable devices (traditionally software based) and a powerf...
Michele Borgatti, Andrea Capello, Umberto Rossi, J...
DATE
2004
IEEE
130views Hardware» more  DATE 2004»
14 years 12 days ago
Dynamic Power Management Using Data Buffers
This paper presents a method to reduce energy consumption by inserting data buffers. The method determines whether power can be reduced by inserting a buffer between two component...
Le Cai, Yung-Hsiang Lu
DATE
2004
IEEE
129views Hardware» more  DATE 2004»
14 years 12 days ago
Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach
Future Systems-on-Chips will include multiple heterogeneous processing units, with complex data-dependent shared resource access patterns dictating the performance of a design. Cu...
Alex Bobrek, Joshua J. Pieper, Jeffrey E. Nelson, ...
DATE
2004
IEEE
121views Hardware» more  DATE 2004»
14 years 12 days ago
Experiences during the Experimental Validation of the Time-Triggered Architecture
During last years, the Time-Triggered Architecture (TTA) has been gaining acceptance as a generic architecture for highly dependable real-time systems. It is now being used to imp...
Sara Blanc, Joaquin Gracia, Pedro J. Gil
DATE
2004
IEEE
152views Hardware» more  DATE 2004»
14 years 12 days ago
A Design Methodology for the Exploitation of High Level Communication Synthesis
In this paper we analyse some methodological concerns that have to be faced in a design flow which contains automatic synthesis phases from high-level, system descriptions. In par...
Francesco Bruschi, Massimo Bombana
DATE
2004
IEEE
133views Hardware» more  DATE 2004»
14 years 12 days ago
Channel Decoder Architecture for 3G Mobile Wireless Terminals
Channel coding is a key element of any digital wireless communication system since it minimizes the effects of noise and interference on the transmitted signal. In thirdgeneration...
Friedbert Berens, Gerd Kreiselmaier, Norbert Wehn
DATE
2004
IEEE
138views Hardware» more  DATE 2004»
14 years 12 days ago
STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores
This paper presents STEPS, an innovative softwarebased approach for testing P1500-compliant SoCs. STEPS is based on the concept that the ATE is not considered as an initiator appl...
Mounir Benabdenbi, Alain Greiner, François ...