Sciweavers

ICCAD
1997
IEEE
101views Hardware» more  ICCAD 1997»
14 years 29 days ago
Optimal wire and transistor sizing for circuits with non-tree topology
Lieven Vandenberghe, Stephen P. Boyd, Abbas El Gam...
ICCAD
1997
IEEE
105views Hardware» more  ICCAD 1997»
14 years 29 days ago
Fast field solver-programs for thermal and electrostatic analysis of microsystem elements
To solve the problem of fast thermal and electrostatic simulation of microsystem elements two different field solver tools have been developed at TUB. The µSTHERMANAL program is ...
Vladimir Székely, Márta Rencz
ICCAD
1997
IEEE
71views Hardware» more  ICCAD 1997»
14 years 29 days ago
Timing analysis based on primitive path delay fault identification
Mukund Sivaraman, Andrzej J. Strojwas
ICCAD
1997
IEEE
84views Hardware» more  ICCAD 1997»
14 years 29 days ago
Global harmony: coupled noise analysis for full-chip RC interconnect networks
Kenneth L. Shepard, Vinod Narayanan, Peter C. Elme...
ICCAD
1997
IEEE
133views Hardware» more  ICCAD 1997»
14 years 29 days ago
Functional simulation using binary decision diagrams
In many veri cation techniques fast functional evaluation of a Boolean network is needed. We investigate the idea of using Binary Decision Diagrams BDDs for functional simulatio...
Christoph Scholl, Rolf Drechsler, Bernd Becker
ICCAD
1997
IEEE
101views Hardware» more  ICCAD 1997»
14 years 29 days ago
NRG: global and detailed placement
We present a new approach to the placement problem. The proposed approach consists of analyzing the input circuit and deciding on a two-dimensional global grid for that particular...
Majid Sarrafzadeh, Maogang Wang
ICCAD
1997
IEEE
147views Hardware» more  ICCAD 1997»
14 years 29 days ago
Built-in test generation for synchronous sequential circuits
We consider the problem of built-in test generation for synchronous sequential circuits. The proposed scheme leaves the circuit flip-flops unmodified, and thus allows at-speed ...
Irith Pomeranz, Sudhakar M. Reddy
ICCAD
1997
IEEE
144views Hardware» more  ICCAD 1997»
14 years 29 days ago
Exploiting off-chip memory access modes in high-level synthesis
Memory-intensive behaviors often contain large arrays that are synthesized into off-chip memories. With the increasing gap between on-chip and off-chip memory access delays, it is...
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nico...