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ICCAD
1997
IEEE
103views Hardware» more  ICCAD 1997»
14 years 29 days ago
Delay bounded buffered tree construction for timing driven floorplanning
Maggie Zhiwei Kang, Wayne Wei-Ming Dai, Tom Dillin...
ICCAD
1997
IEEE
129views Hardware» more  ICCAD 1997»
14 years 29 days ago
A fast and robust exact algorithm for face embedding
We present a new matrix formulation of the face hypercube embedding problem that motivates the design of an efficient search strategy to find an encoding that satisfies all fac...
Evguenii I. Goldberg, Tiziano Villa, Robert K. Bra...
ICCAD
1997
IEEE
108views Hardware» more  ICCAD 1997»
14 years 29 days ago
Negative thinking by incremental problem solving: application to unate covering
We introduce a new technique to solve exactly a discrete optimization problem, based on the paradigm of “negative” thinking. The motivation is that when searching the space of...
Evguenii I. Goldberg, Luca P. Carloni, Tiziano Vil...
ICCAD
1997
IEEE
142views Hardware» more  ICCAD 1997»
14 years 29 days ago
Library-less synthesis for static CMOS combinational logic circuits
Traditional synthesis techniques optimize CMOS circuits in two phases i) logic minimization and ii) library mapping phase. Typically, the structures and the sizes of the gates in ...
Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullel...
ICCAD
1997
IEEE
127views Hardware» more  ICCAD 1997»
14 years 29 days ago
OPTIMIST: state minimization for optimal 2-level logic implementation
We present a novel method for state minimization of incompletely-specified finite state machines. Where classic methods simply minimize the number of states, ours directly addre...
Robert M. Fuhrer, Steven M. Nowick
ICCAD
1997
IEEE
83views Hardware» more  ICCAD 1997»
14 years 29 days ago
Replication for logic bipartitioning
Logic replication, the duplication of logic in order to limit communication between partitions, is an effective part of a complete partitioning solution. In this paper we seek a b...
Morgan Enos, Scott Hauck, Majid Sarrafzadeh
ICCAD
1997
IEEE
90views Hardware» more  ICCAD 1997»
14 years 29 days ago
A hierarchical decomposition methodology for multistage clock circuits
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar
ICCAD
1997
IEEE
100views Hardware» more  ICCAD 1997»
14 years 29 days ago
Decomposition and technology mapping of speed-independent circuits using Boolean relations
Jordi Cortadella, Michael Kishinevsky, Alex Kondra...