Sciweavers

DATE
1997
IEEE
107views Hardware» more  DATE 1997»
14 years 1 months ago
Acceleration of behavioral simulation on simulation specific machines
Behavioral simulation is faster than gate-level logic simulation, however, the simulation speed is too slow for large systems. Simulation specific machines accelerated simulation ...
Minoru Shoji, Fumiyasu Hirose, Shintaro Shimogori,...
DATE
1997
IEEE
97views Hardware» more  DATE 1997»
14 years 1 months ago
Analysis of 3D conjugate heat transfers in electronics
An efficient method for the analysis of real 3D conjugate heat transfer for electronic devices is presented. This methodology is based on the coupling of two software : a conducti...
J. P. Fradin, L. Molla, B. Desaunettes
DATE
1997
IEEE
67views Hardware» more  DATE 1997»
14 years 1 months ago
A constructive approach towards correctness of synthesis-application within retiming
Dirk Eisenbiegler, Ramayya Kumar, Christian Blumen...
DATE
1997
IEEE
106views Hardware» more  DATE 1997»
14 years 1 months ago
A CMOS low-voltage, high-gain op-amp
Guo-Neng Lu, Gerard Sou
DATE
1997
IEEE
109views Hardware» more  DATE 1997»
14 years 1 months ago
Cartesian multipole based numerical integration for 3D capacitance extraction
Application of the hierarchical Schur algorithm to the boundary element method for 3D capacitance extraction shifts the speed bottleneck from inversion of the influence matrix to...
U. Geigenmüller, N. P. van der Meijs
DATE
1997
IEEE
66views Hardware» more  DATE 1997»
14 years 1 months ago
Microsystem design using simulator coupling
S. Wünsche, C. Clauss, P. Schwarz, Frank Wink...
DATE
1997
IEEE
84views Hardware» more  DATE 1997»
14 years 1 months ago
Built-in self-test methodology for A/D converters
A (partial) Built-In Self-Test (BIST) methodology is proposed for analog to digital (MD)converters. In this methodology the number of bits of the A/Dconverter that needs to be mon...
R. de Vries, Taco Zwemstra, E. M. J. G. Bruls, Pau...
DATE
1997
IEEE
58views Hardware» more  DATE 1997»
14 years 1 months ago
On the way to the 2.5 Gbits/s ATM network ATM multiplexer demultiplexer ASIC
J. Riesco, J. C. Diaz, L. A. Merayo, J. L. Conesa,...
DATE
1997
IEEE
75views Hardware» more  DATE 1997»
14 years 1 months ago
Random benchmark circuits with controlled attributes
Two major improvements, controlled fan-in and automated initial-circuit production, were made over the random generator of benchmark circuits presented at DAC'94. This is an ...
Kazuo Iwama, Kensuke Hino, Hiroyuki Kurokawa, Suna...