ATS
1997
IEEE
14 years 1 months ago
1997
IEEE
ASYNC
1997
IEEE
14 years 1 months ago
1997
IEEE
This paper introduces a novel technique for synthesis of speed-independent circuits from their Signal Transition Graph specifications. The new method uses partial order in the fo...
ASYNC
1997
IEEE
14 years 1 months ago
1997
IEEE
This paper presents an in-depth case study in highperformance asynchronous adder design. A recent method, called “speculative completion”, is used. This method uses single-rai...
ASYNC
1997
IEEE
14 years 1 months ago
1997
IEEE
ASYNC
1997
IEEE
14 years 1 months ago
1997
IEEE
The realisation of Delay-Insensitive (DI) asynchronous circuits with a CMOS ternary logic is described in this paper. The main advantage of temary logic is the easy realisation of...
ASYNC
1997
IEEE
14 years 1 months ago
1997
IEEE
ASYNC
1997
IEEE
14 years 1 months ago
1997
IEEE
ASAP
1997
IEEE
14 years 1 months ago
1997
IEEE
This paper presents how to find optimized buffer size for VLSI architectures of full-search block matching algorithms. Starting from the DG (dependency graph) analysis, we focus i...
ASAP
1997
IEEE
14 years 1 months ago
1997
IEEE
ASAP
1997
IEEE
14 years 1 months ago
1997
IEEE