ISCA
2010
IEEE
14 years 2 months ago
2010
IEEE
ISCA
2010
IEEE
14 years 2 months ago
2010
IEEE
SIMD organizations amortize the area and power of fetch, decode, and issue logic across multiple processing units in order to maximize throughput for a given area and power budget...
ISCA
2010
IEEE
14 years 2 months ago
2010
IEEE
Next generation tiled microarchitectures are going to be limited by off-chip misses and by on-chip network usage. Furthermore, these platforms will run an heterogeneous mix of ap...
ISCA
2010
IEEE
14 years 2 months ago
2010
IEEE
Previous research has shown that Staged Execution (SE), i.e., dividing a program into segments and executing each segment at the core that has the data and/or functionality to bes...
ISCA
2010
IEEE
14 years 2 months ago
2010
IEEE
In this paper, we propose ColorSafe, an architecture that detects and dynamically avoids single- and multi-variable atomicity violation bugs. The key idea is to group related data...
ISCA
2010
IEEE
14 years 2 months ago
2010
IEEE
Numerous studies have shown that datacenter computers rarely operate at full utilization, leading to a number of proposals for creating servers that are energy proportional with r...
ISCA
2010
IEEE
14 years 2 months ago
2010
IEEE
ISCA
2010
IEEE
14 years 2 months ago
2010
IEEE
Aggressive technology scaling into the nanometer regime has led to a host of reliability challenges in the last several years. Unlike onchip caches, which can be efficiently prot...
ISCA
2010
IEEE
14 years 2 months ago
2010
IEEE
DRAM vendors have traditionally optimized the cost-perbit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, wher...
ISCA
2010
IEEE
14 years 2 months ago
2010
IEEE
As CMOS scales beyond the 45nm technology node, leakage concerns are starting to limit microprocessor performance growth. To keep dynamic power constant across process generations...