DATE
2003
IEEE
14 years 2 months ago
2003
IEEE
More and more the system verification makes use of hardware emulation techniques that allow a speed up in simulation performance up to thousand times. Typically, a design is comp...
DATE
2003
IEEE
14 years 2 months ago
2003
IEEE
DATE
2003
IEEE
14 years 2 months ago
2003
IEEE
This work presents a soft IP description of Rijndael, the Advanced Encryption Standard (AES) of National Institute of Standards and Technology (NIST). This Rijndael implementation...
DATE
2003
IEEE
14 years 2 months ago
2003
IEEE
The first non-enumerative framework for diagnosing path delay faults using zero suppressed binary decision diagrams is introduced. We show that fault free path delay faults with ...
DATE
2003
IEEE
14 years 2 months ago
2003
IEEE
In this article we propose a high speed and highly testable parallel two-rail code checker, which features a compact structure and is Totally-Self-Checking or Strongly Code-Disjoi...
DATE
2003
IEEE
14 years 2 months ago
2003
IEEE
There have been several recent attempts to include duplication-based on-line testability in behaviourally synthesized designs. In this paper, on-line testability is considered wit...
DATE
2003
IEEE
14 years 2 months ago
2003
IEEE
We propose a method for local search of Boolean relations relating variables of a CNF formula. The method is to branch on small subsets of the set of CNF variables and to analyze ...
DATE
2003
IEEE
14 years 2 months ago
2003
IEEE
Test pattern decompression techniques are bounded with the algorithm of test pattern ordering and test data flow controlling. Some of the methods could have more sophisticated sor...
DATE
2003
IEEE
14 years 2 months ago
2003
IEEE
In Networks on Chip, NoC, very low cost and high performance switches will be of critical importance. For a regular two-dimensional NoC we propose a very simple, memoryless switch...
DATE
2003
IEEE
14 years 2 months ago
2003
IEEE
We present a high-level synthesis algorithm solving the combined scheduling, allocation and binding problem minimizing area under both latency and maximum power per clock-cycle co...