ASYNC
2003
IEEE
14 years 2 months ago
2003
IEEE
We present a high-speed, clockless, serial link transceiver for inter-chip communication in asynchronous VLSI systems. Serial link transceivers achieve high offchip data rates by ...
ASYNC
2003
IEEE
14 years 2 months ago
2003
IEEE
High-speed asynchronous ripple FIFOs may be easily embedded in synchronous environments and can elegantly handle the problem of forwarding data between clock domains. In cases whe...
ASYNC
2003
IEEE
14 years 2 months ago
2003
IEEE
We present a Sensor-Network Asynchronous Processor (SNAP), which we have designed to be both a processor core for a sensor-network node and a component of a chip multiprocessor, t...
ASYNC
2003
IEEE
14 years 2 months ago
2003
IEEE
ASYNC
2003
IEEE
14 years 2 months ago
2003
IEEE
We present the design of a high performance on-chip pipelined asynchronous DRAM suitable for use in a microprocessor cache. Although traditional DRAM structures suffer from long a...
ACSD
2003
IEEE
14 years 2 months ago
2003
IEEE
ACSD
2003
IEEE
14 years 2 months ago
2003
IEEE
ACSD
2003
IEEE
14 years 2 months ago
2003
IEEE
Signal Transition Graphs (STGs) are one of the most popular models for the specification of asynchronous circuits. A STG can be implemented if it admits a so-called consistent an...
ACSD
2003
IEEE
14 years 2 months ago
2003
IEEE
Message Sequence Charts (MSC) have been traditionally used to depict execution scenarios in the early stages of design cycle. MSCs portray inter-process ( inter-object) interactio...
ACSD
2003
IEEE
14 years 2 months ago
2003
IEEE
