Sciweavers

ATS
2003
IEEE
93views Hardware» more  ATS 2003»
14 years 2 months ago
Optimal System-on-Chip Test Scheduling
1 In this paper, we show that the scheduling of tests on the test access mechanism (TAM) is equivalent to independent job scheduling on identical machines and we make use of an exi...
Erik Larsson, Hideo Fujiwara
ATS
2003
IEEE
76views Hardware» more  ATS 2003»
14 years 2 months ago
STAGE: A Decoding Engine Suitable for Multi-Compressed Test Data
: Most of the recently discussed test stimulus data compression techniques are based on the low care bit densities found in typical scan test vectors. Data reduction primarily is a...
Bernd Koenemann
ATS
2003
IEEE
84views Hardware» more  ATS 2003»
14 years 2 months ago
Test Time Minimization for Hybrid BIST of Core-Based Systems
Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, ...
ATS
2003
IEEE
87views Hardware» more  ATS 2003»
14 years 2 months ago
March SL: A Test For All Static Linked Memory Faults
The analysis of linked faults has proven to be a source for new memory tests, characterized by an increased fault coverage. The paper gives a set of five new tests to target all ...
Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mik...
ATS
2003
IEEE
106views Hardware» more  ATS 2003»
14 years 2 months ago
Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders
Luigi Dilillo, Patrick Girard, Serge Pravossoudovi...
ATS
2003
IEEE
126views Hardware» more  ATS 2003»
14 years 2 months ago
Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces
Abstract: As a result of variations in the fabrication process, different memory components are produced with different operational characteristics, a situation that complicates th...
Zaid Al-Ars, A. J. van de Goor
ASYNC
2003
IEEE
97views Hardware» more  ASYNC 2003»
14 years 2 months ago
Energy and Performance Models for Clocked and Asynchronous Communication
Parameterized first-order models for throughput, energy, and bandwidth are presented in this paper. Models are developed for many common pipeline methodologies, including clocked...
Kenneth S. Stevens
ASYNC
2003
IEEE
93views Hardware» more  ASYNC 2003»
14 years 2 months ago
On the Existence of Hazard-Free Multi-Level Logic
Steven M. Nowick, Charles W. O'Donnell
ASYNC
2003
IEEE
93views Hardware» more  ASYNC 2003»
14 years 2 months ago
The Lutonium: A Sub-Nanojoule Asynchronous 8051 Microcontroller
We describe the Lutonium, an asynchronous 8051 microcontroller designed for optimal ؾ . In 0.18- m CMOS, at nominal
Alain J. Martin, Mika Nyström, Karl Papadanto...
ASYNC
2003
IEEE
73views Hardware» more  ASYNC 2003»
14 years 2 months ago
Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems
The lack of proven mechanisms for transferring data between multiple synchronous islands has been a major impediment for applying globally asynchronous locally synchronous (GALS) ...
Thomas Villiger, Hubert Kaeslin, Frank K. Gür...