DATE
2003
IEEE
14 years 2 months ago
2003
IEEE
The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing anal...
DATE
2003
IEEE
14 years 2 months ago
2003
IEEE
This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-...
CEC
2003
IEEE
14 years 2 months ago
2003
IEEE
Evolvable hardware adjusts oneself to changeable environments by self-organizing the circuit. Due to its high productivity and creativity for designing circuit, it is widely invest...
ATS
2003
IEEE
14 years 2 months ago
2003
IEEE
Domain testing is a well-known software testing technique. Although research tasks have been initiated in domain testing, automatic test data generation based on character string ...
ATS
2003
IEEE
14 years 2 months ago
2003
IEEE
We present a framework for high-level design validation using an efficient register-transfer level (RTL) automatic test pattern generator (ATPG). The RTL ATPG generates the test ...
ATS
2003
IEEE
14 years 2 months ago
2003
IEEE
Recent probabilistic test generation approaches have proven that detecting single stuck-at faults multiple times is effective at reducing the defective part level (DPL). Unfortuna...
ATS
2003
IEEE
14 years 2 months ago
2003
IEEE
Capacitive crosstalk can give rise to slowdown of signals that can propagate to a circuit output and create a functional error. A test generation methodology, called XGEN, was dev...
ATS
2003
IEEE
14 years 2 months ago
2003
IEEE
Software-based self-testing is a promising approach for the testing of processor cores which are embedded inside a System-on-a-Chip (SoC), as it can apply test vectors in function...
ATS
2003
IEEE
14 years 2 months ago
2003
IEEE
A new technique for synthesizing totally symmetric Boolean functions is presented that achieves complete robust path delay fault testability. We apply BDDs for the synthesis of sy...
ATS
2003
IEEE
14 years 2 months ago
2003
IEEE
Fault diagnosis of full-scan designs has been progressed significantly. However, most existing techniques are aimed at a logic block with a single fault. Strategies on top of thes...