Sciweavers

ECBS
2010
IEEE
146views Hardware» more  ECBS 2010»
14 years 2 months ago
Design-Space Exploration through Constraint-Based Model-Transformation
Abstract—Many design steps during system development like functional partitioning, refactoring of the architecture, or the mapping to the platform - can be understood as an explo...
Bernhard Schätz, Florian Hölzl, Torbj&ou...
ECBS
2010
IEEE
147views Hardware» more  ECBS 2010»
14 years 2 months ago
Supporting Customizable Architectural Design Decision Management
—When engineering complex software systems, the key Architectural Design Decisions (ADD) and the reasoning underlying those decisions need to be fully understood by all stakehold...
Lianping Chen, Muhammad Ali Babar
ECBS
2010
IEEE
151views Hardware» more  ECBS 2010»
14 years 2 months ago
Generating Test Plans for Acceptance Tests from UML Activity Diagrams
The Unified Modeling Language (UML) is the standard to specify the structure and behaviour of software systems. The created models are a constitutive part of the software speci...
Andreas Heinecke, Tobias Brückmann, Tobias Gr...
PACS
2004
Springer
112views Hardware» more  PACS 2004»
14 years 2 months ago
Low-Overhead Core Swapping for Thermal Management
Technology scaling trends and the limitations of packaging and cooling have intensified the need for thermally efficient architectures and architecture-level temperature managemen...
Eren Kursun, Glenn Reinman, Suleyman Sair, Anahita...
PACS
2004
Springer
146views Hardware» more  PACS 2004»
14 years 2 months ago
An Optimized Front-End Physical Register File with Banking and Writeback Filtering
In recent years, processor manufacturers have converged on two types of register file architectures. Both IBM with its POWER series and Intel with its Pentium series are using a ...
Miquel Pericàs, Rubén Gonzále...
PACS
2004
Springer
128views Hardware» more  PACS 2004»
14 years 2 months ago
Erratum
PACS
2004
Springer
115views Hardware» more  PACS 2004»
14 years 2 months ago
Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization
Dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The delay ...
Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose, ...
PACS
2004
Springer
166views Hardware» more  PACS 2004»
14 years 2 months ago
Context-Independent Codes for Off-Chip Interconnects
Abstract. This paper introduces the concept of context-independent coding using frequency-based mapping schemes in order to reduce off-chip interconnect power consumption. State-of...
Kartik Mohanram, Scott Rixner
PACS
2004
Springer
306views Hardware» more  PACS 2004»
14 years 2 months ago
Power Consumption Breakdown on a Modern Laptop
The purpose of this work was to obtain a componentwise breakdown of the power consumption a modern laptop. We measured the power usage of the key components in an IBM ThinkPad R40...
Aqeel Mahesri, Vibhore Vardhan
PACS
2004
Springer
102views Hardware» more  PACS 2004»
14 years 2 months ago
Bit-Sliced Datapath for Energy-Efficient High Performance Microprocessors
Sumeet Kumar, Prateek Pujara, Aneesh Aggarwal