System-on-Chip devices containing both conventional and reconfigurable circuits are increasing in popularity. However the on-chip debug support infrastructure required to aid syst...
This paper proposes a new approach for the hazard checking of timed asynchronous circuits. Previous papers proposed either exact algorithms, which suffer from statespace explosion...
Adoption of the 10GbE Ethernet standard has been impeded by two important performance-oriented considerations: 1) processing requirements of common protocol stacks and 2) end-to-e...
In this paper, an adaptive wormhole router for a flexible on-chip interconnection network is proposed and implemented for a Chip-Multi Processor (CMP). It adopts a wormhole switc...
The necessity of devising novel thread-level speculation (TLS) techniques has become extremely important with the growing acceptance of multi-core architectures by the industry. H...
Bioinformatics is among the most active research areas in computer science. In this study, we investigate a suite of workloads in bioinformatics on two multiprocessor systems with...
We present node level primitives for parallel exact inference on an arbitrary Bayesian network. We explore the probability representation on each node of Bayesian networks and eac...
One way to exploit Thread Level Parallelism (TLP) is to use architectures that implement novel multithreaded execution models, like Scheduled DataFlow (SDF). This latter model pro...
Code Compression has been used to alleviate the memory requirements as well as to improve performance and/or minimize energy consumption. On the other hand, implementing security ...
Eduardo Wanderley Netto, Romain Vaslin, Guy Gognia...