Sciweavers

AHS
2007
IEEE
231views Hardware» more  AHS 2007»
14 years 3 months ago
Debug Support for Hybrid SoCs
System-on-Chip devices containing both conventional and reconfigurable circuits are increasing in popularity. However the on-chip debug support infrastructure required to aid syst...
Andrew B. T. Hopkins, Klaus D. McDonald-Maier
ACSD
2007
IEEE
67views Hardware» more  ACSD 2007»
14 years 3 months ago
Hazard Checking of Timed Asynchronous Circuits Revisited
This paper proposes a new approach for the hazard checking of timed asynchronous circuits. Previous papers proposed either exact algorithms, which suffer from statespace explosion...
Frédéric Béal, Tomohiro Yoned...
SBACPAD
2007
IEEE
110views Hardware» more  SBACPAD 2007»
14 years 3 months ago
Architectural Breakdown of End-to-End Latency in a TCP/IP Network
Adoption of the 10GbE Ethernet standard has been impeded by two important performance-oriented considerations: 1) processing requirements of common protocol stacks and 2) end-to-e...
Steen Larsen, Parthasarathy Sarangam, Ram Huggahal...
SBACPAD
2007
IEEE
130views Hardware» more  SBACPAD 2007»
14 years 3 months ago
Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP)
In this paper, an adaptive wormhole router for a flexible on-chip interconnection network is proposed and implemented for a Chip-Multi Processor (CMP). It adopts a wormhole switc...
Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh
SBACPAD
2007
IEEE
129views Hardware» more  SBACPAD 2007»
14 years 3 months ago
Predicting Loop Termination to Boost Speculative Thread-Level Parallelism in Embedded Applications
The necessity of devising novel thread-level speculation (TLS) techniques has become extremely important with the growing acceptance of multi-core architectures by the industry. H...
Md. Mafijul Islam
SBACPAD
2007
IEEE
91views Hardware» more  SBACPAD 2007»
14 years 3 months ago
Impacts of Multiprocessor Configurations on Workloads in Bioinformatics
Bioinformatics is among the most active research areas in computer science. In this study, we investigate a suite of workloads in bioinformatics on two multiprocessor systems with...
Youfeng Wu, Mauricio Breternitz Jr., Victor Ying
SBACPAD
2007
IEEE
128views Hardware» more  SBACPAD 2007»
14 years 3 months ago
Node Level Primitives for Parallel Exact Inference
We present node level primitives for parallel exact inference on an arbitrary Bayesian network. We explore the probability representation on each node of Bayesian networks and eac...
Yinglong Xia, Viktor K. Prasanna
SBACPAD
2007
IEEE
121views Hardware» more  SBACPAD 2007»
14 years 3 months ago
DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems
One way to exploit Thread Level Parallelism (TLP) is to use architectures that implement novel multithreaded execution models, like Scheduled DataFlow (SDF). This latter model pro...
Roberto Giorgi, Zdravko Popovic, Nikola Puzovic
SBACPAD
2007
IEEE
554views Hardware» more  SBACPAD 2007»
14 years 3 months ago
Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded Processors
Rafael Ubal, Julio Sahuquillo, Salvador Petit, Ped...
SBACPAD
2007
IEEE
143views Hardware» more  SBACPAD 2007»
14 years 3 months ago
A Code Compression Method to Cope with Security Hardware Overheads
Code Compression has been used to alleviate the memory requirements as well as to improve performance and/or minimize energy consumption. On the other hand, implementing security ...
Eduardo Wanderley Netto, Romain Vaslin, Guy Gognia...