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FPL
2007
Springer
106views Hardware» more  FPL 2007»
14 years 3 months ago
Monte Carlo Logarithmic Number System for Model Predictive Control
Simple algorithms can be analytically characterized, but such analysis is questionable or even impossible for more complicated algorithms, such as Model Predictive Control (MPC). ...
Panagiotis D. Vouzis, Sylvain Collange, Mark G. Ar...
FPL
2007
Springer
121views Hardware» more  FPL 2007»
14 years 3 months ago
Improving Pipelined Soft Processors with Multithreading
Designers of FPGA-based systems are increasingly including soft processors—processors implemented in programmable logic—in their designs. Any combination of area, clock freque...
Martin Labrecque, J. Gregory Steffan
FPL
2007
Springer
96views Hardware» more  FPL 2007»
14 years 3 months ago
Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core
This paper describes the mapping of a two-dimensional inverse discrete cosine transform (2-D IDCT) onto a wordlevel reconfigurable Montium R processor. This shows that the IDCT i...
Lodewijk T. Smit, Gerard K. Rauwerda, Albert Molde...
FPL
2007
Springer
137views Hardware» more  FPL 2007»
14 years 3 months ago
Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA
Multiprocessor systems-on-chip (MPSoC) are being developed in increasing numbers to support the high number of applications running on modern embedded systems. Designing and progr...
Akash Kumar, Shakith Fernando, Yajun Ha, Bart Mesm...
FPL
2007
Springer
146views Hardware» more  FPL 2007»
14 years 3 months ago
Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips
The complexity of today’s embedded applications requires modern high-performance embedded System-on-Chip (SoC) platforms to be multiprocessor architectures. Advances in FPGA tec...
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere
FPL
2007
Springer
105views Hardware» more  FPL 2007»
14 years 3 months ago
An Execution Model for Hardware/Software Compilation and its System-Level Realization
We introduce a new execution model for orchestrating the interaction between the conventional processor and the reconfigurable compute unit in adaptive computer systems. We then ...
Holger Lange, Andreas Koch
FPL
2007
Springer
127views Hardware» more  FPL 2007»
14 years 3 months ago
Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications
This paper presents a novel architecture for domain-specific FPGA devices. This architecture can be optimised for both speed and density by exploiting domain-specific informatio...
Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wa...
FPL
2007
Springer
106views Hardware» more  FPL 2007»
14 years 3 months ago
RAMP Blue: A Message-Passing Manycore System in FPGAs
We are developing a set of reusable design blocks and several prototype systems for emulation of multi-core architectures in FPGAs. RAMP Blue is the first of these prototypes and...
Alex Krasnov, Andrew Schultz, John Wawrzynek, Greg...
FPL
2007
Springer
136views Hardware» more  FPL 2007»
14 years 3 months ago
A Load/Store Unit for a Memcpy Hardware Accelerator
Recently, a dedicated hardware accelerator was proposed that works in conjunction with caches found next to modern-day microprocessors, to speedup the commonly utilized memcpy ope...
Stamatis Vassiliadis, Filipa Duarte, Stephan Wong