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SBACPAD
2007
IEEE
85views Hardware» more  SBACPAD 2007»
14 years 3 months ago
Exigency-based real-time scheduling policy to provide absolute QoS for web services
— Telemedicine, distance learning and e-commerce applications impose time constraints directly related to the efficacy of their operations. In order to offer reliability levels ...
Lucas S. Casagrande, Rodrigo Fernandes de Mello, R...
SBACPAD
2007
IEEE
157views Hardware» more  SBACPAD 2007»
14 years 3 months ago
Exploring Novel Parallelization Technologies for 3-D Imaging Applications
Multi-dimensional imaging techniques involve the processing of high resolution images commonly used in medical, civil and remote-sensing applications. A barrier commonly encounter...
Diego Rivera, Dana Schaa, Micha Moffie, David R. K...
MTV
2007
IEEE
166views Hardware» more  MTV 2007»
14 years 3 months ago
Application of Automated Model Generation Techniques to Analog/Mixed-Signal Circuits
Abstract—Abstract models of analog/mixed-signal (AMS) circuits can be used for formal verification and system-level simulation. The difficulty of creating these models preclude...
Scott Little, Alper Sen, Chris J. Myers
MTV
2007
IEEE
121views Hardware» more  MTV 2007»
14 years 3 months ago
Chico: An On-chip Hardware Checker for Pipeline Control Logic
The widening gap between CPU complexity and verification capability is becoming increasingly more salient. It is impossible to completely verify the functionality of a modern mic...
Andrew DeOrio, Adam Bauserman, Valeria Bertacco
MTV
2007
IEEE
118views Hardware» more  MTV 2007»
14 years 3 months ago
Reduction of Power Dissipation during Scan Testing by Test Vector Ordering
Test vector ordering is recognized as a simple and non-intrusive approach to assist test power reduction. Simulation based test vector ordering approach to minimize circuit transit...
Wang-Dauh Tseng, Lung-Jen Lee
MICRO
2007
IEEE
135views Hardware» more  MICRO 2007»
14 years 3 months ago
Microarchitectural Design Space Exploration Using an Architecture-Centric Approach
The microarchitectural design space of a new processor is too large for an architect to evaluate in its entirety. Even with the use of statistical simulation, evaluation of a sing...
Christophe Dubach, Timothy M. Jones, Michael F. P....
MICRO
2007
IEEE
188views Hardware» more  MICRO 2007»
14 years 3 months ago
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding
In deep sub-micron ICs, growing amounts of ondie memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. As scaling progresses...
Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Fal...
MICRO
2007
IEEE
94views Hardware» more  MICRO 2007»
14 years 3 months ago
Argus: Low-Cost, Comprehensive Error Detection in Simple Cores
We have developed Argus, a novel approach for providing low-cost, comprehensive error detection for simple cores. The key to Argus is that the operation of a von Neumann core cons...
Albert Meixner, Michael E. Bauer, Daniel J. Sorin
MICRO
2007
IEEE
137views Hardware» more  MICRO 2007»
14 years 3 months ago
Implementing Signatures for Transactional Memory
Transactional Memory (TM) systems must track the read and write sets—items read and written during a transaction—to detect conflicts among concurrent transactions. Several TM...
Daniel Sanchez, Luke Yen, Mark D. Hill, Karthikeya...
MICRO
2007
IEEE
129views Hardware» more  MICRO 2007»
14 years 3 months ago
A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed techniques for coherence traffic reduct...
Jason Zebchuk, Elham Safi, Andreas Moshovos