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SBACPAD
2008
IEEE
126views Hardware» more  SBACPAD 2008»
14 years 3 months ago
A Software Transactional Memory System for an Asymmetric Processor Architecture
Due to the advent of multi-core processors and the consequent need for better concurrent programming abstractions, new synchronization paradigms have emerged. A promising one, kno...
Felipe Goldstein, Alexandro Baldassin, Paulo Cento...
SBACPAD
2008
IEEE
127views Hardware» more  SBACPAD 2008»
14 years 3 months ago
Measuring Operating System Overhead on CMT Processors
Numerous studies have shown that Operating System (OS) noise is one of the reasons for significant performance degradation in clustered architectures. Although many studies exami...
Petar Radojkovic, Vladimir Cakarevic, Javier Verd&...
SBACPAD
2008
IEEE
170views Hardware» more  SBACPAD 2008»
14 years 3 months ago
Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...
James Poe, Chang-Burm Cho, Tao Li
SBACPAD
2008
IEEE
100views Hardware» more  SBACPAD 2008»
14 years 3 months ago
Selection of the Register File Size and the Resource Allocation Policy on SMT Processors
The performance impact of the Physical Register File (PRF) size on Simultaneous Multithreading processors has not been extensively studied in spite of being a critical shared reso...
Jesús Alastruey, Teresa Monreal, Francisco ...
SASP
2008
IEEE
153views Hardware» more  SASP 2008»
14 years 3 months ago
TRaX: A Multi-Threaded Architecture for Real-Time Ray Tracing
Ray tracing is a technique used for generating highly realistic computer graphics images. In this paper, we explore the design of a simple but extremely parallel, multi-threaded, ...
Josef B. Spjut, Solomon Boulos, Daniel Kopta, Erik...
SASP
2008
IEEE
77views Hardware» more  SASP 2008»
14 years 3 months ago
Resource Sharing in Custom Instruction Set Extensions
Abstract—Customised processor performance generally increases as additional custom instructions are added. However, performance is not the only metric that modern systems must ta...
Marcela Zuluaga, Nigel P. Topham
SASP
2008
IEEE
95views Hardware» more  SASP 2008»
14 years 3 months ago
Extensible On-Chip Peripherals
Bharat Sukhwani, Alessandro Forin, Richard Neil Pi...
SASP
2008
IEEE
94views Hardware» more  SASP 2008»
14 years 3 months ago
An MDCT Hardware Accelerator for MP3 Audio
— With the increasing popularity of MP3 audio, there is a need to develop cost and power efficient architectures for the MP3 encoder and decoder. This paper describes dedicated ...
Xingdong Dai, Meghanad D. Wagh
SASP
2008
IEEE
101views Hardware» more  SASP 2008»
14 years 3 months ago
Custom Processor Core Construction from C Code
—In this paper we present a method for construction of application specific processor cores from a given C code. Our approach consists of three phases. We start by quantifying t...
Jelena Trajkovic, Daniel D. Gajski
SASP
2008
IEEE
164views Hardware» more  SASP 2008»
14 years 3 months ago
AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications
This paper proposes an energy efficient processor which can be used as a design alternative for the dynamic voltage scaling (DVS) processors in embedded system design. The proces...
Tohru Ishihara, Seiichiro Yamaguchi, Yuriko Ishito...