MICRO
2008
IEEE
14 years 3 months ago
2008
IEEE
—Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent f...
MICRO
2008
IEEE
14 years 3 months ago
2008
IEEE
The advent of multicores presents a promising opportunity for speeding up sequential programs via profile-based speculative parallelization of these programs. In this paper we pr...
MICRO
2008
IEEE
14 years 3 months ago
2008
IEEE
As chip multiprocessors scale to a greater number of processing cores, on-chip interconnection networks will experience dramatic increases in both bandwidth demand and power dissi...
MICRO
2008
IEEE
14 years 3 months ago
2008
IEEE
—L1 instruction-cache misses pose a critical performance bottleneck in commercial server workloads. Cache access latency constraints preclude L1 instruction caches large enough t...
MICRO
2008
IEEE
14 years 3 months ago
2008
IEEE
Processors progressively age during their service life due to normal workload activity. Such aging results in gradually slower circuits. Anticipating this fact, designers add timi...
MICRO
2008
IEEE
14 years 3 months ago
2008
IEEE
—Efficient sharing of system resources is critical to obtaining high utilization and enforcing system-level performance objectives on chip multiprocessors (CMPs). Although sever...
MICRO
2008
IEEE
14 years 3 months ago
2008
IEEE
Rootkits have become a growing concern in cyber-security. Typically, they exploit kernel vulnerabilities to gain root privileges of a system and conceal malware’s activities fro...
MICRO
2008
IEEE
14 years 3 months ago
2008
IEEE
Significant improvement to visual quality for real-time 3D graphics requires modeling of complex illumination effects like soft-shadows, reflections, and diffuse lighting intera...
MICRO
2008
IEEE
14 years 3 months ago
2008
IEEE
MICRO
2008
IEEE
14 years 3 months ago
2008
IEEE