In this paper we propose a model to predict the performance of synchronous discrete event simulation. The model considers parameters including the number of active objects per cyc...
In this paper a layout-aware RF synthesis methodology is presented. The methodology combines the power of a differential evolution algorithm with cost function response modeling a...
Peter J. Vancorenland, Geert Van der Plas, Michiel...
SPFDs are a mechanism to express flexibility in Boolean networks. Introduced by Yamashita et al. in the context of FPGA synthesis [4], they were extended later to general combina...
Subarnarekha Sinha, Andreas Kuehlmann, Robert K. B...
- Real-time scheduling on processors that support dynamic voltage and frequency scaling is analyzed. The Slacked Earliest Deadling First (SEDF) algorithm is proposed and it is show...
In this paper, we utilize Rent’s rule as an empirical measure for efficient clustering and placement of circuits on hierarchical FPGAs. We show that careful matching of design c...
Amit Singh, Ganapathy Parthasarathy, Malgorzata Ma...
—In this paper, we present an approach to nonlinear model reduction based on representing a nonlinear system with a piecewise-linear system and then reducing each of the pieces w...
Once the battery becomes fully discharged, a battery-powered portable electronic system goes off-line. Therefore, it is important to take the battery behavior into account. A syst...
The use of nanometer technologies is making it increasingly important to consider transient characteristics of a circuit’s power dissipation (e.g., peak power, and power gradien...