Sciweavers

ICCAD
2001
IEEE
66views Hardware» more  ICCAD 2001»
14 years 9 months ago
Simulation Approaches for Strongly Coupled Interconnect Systems
Joel R. Phillips, Luis Miguel Silveira
ICCAD
2001
IEEE
102views Hardware» more  ICCAD 2001»
14 years 9 months ago
Symbolic Algebra and Timing Driven Data-flow Synthesis
Armita Peymandoust, Giovanni De Micheli
ICCAD
2001
IEEE
108views Hardware» more  ICCAD 2001»
14 years 9 months ago
Placement Driven Retiming with a Coupled Edge Timing Model
Retiming is a widely investigated technique for performance optimization. It performs powerful modifications on a circuit netlist. However, often it is not clear, whether the pred...
Ingmar Neumann, Wolfgang Kunz
ICCAD
2001
IEEE
104views Hardware» more  ICCAD 2001»
14 years 9 months ago
A Symbolic Simulation-Based Methodology for Generating Black-Box Timing Models of Custom Macrocells
We present a methodology for generating black-box timing models for full-custom transistor-level CMOS circuits. Our approach utilizes transistor-level ternary symbolic timing simu...
Clayton B. McDonald, Randal E. Bryant
ICCAD
2001
IEEE
152views Hardware» more  ICCAD 2001»
14 years 9 months ago
Hybrid Structured Clock Network Construction
This paper hierarchically constructs a hybrid mesh/tree clock network structure consisting of overlying zero-skew clock meshes, with underlying zero-skew clock trees originating f...
Haihua Su, Sachin S. Sapatnekar
ICCAD
2001
IEEE
106views Hardware» more  ICCAD 2001»
14 years 9 months ago
System-Level Power/Performance Analysis of Portable Multimedia Systems Communicating over Wireless Channels
This paper presents a new methodology for system-level power and performance analysis of wireless multimedia systems. More precisely, we introduce an analytical approach based on ...
Radu Marculescu, Amit Nandi, Luciano Lavagno, Albe...
ICCAD
2001
IEEE
185views Hardware» more  ICCAD 2001»
14 years 9 months ago
Application-Driven Processor Design Exploration for Power-Performance Trade-off Analysis
1 - This paper presents an efficient design exploration environment for high-end core processors. The heart of the proposed design exploration framework is a two-level simulation e...
Diana Marculescu, Anoop Iyer
ICCAD
2001
IEEE
180views Hardware» more  ICCAD 2001»
14 years 9 months ago
On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits
This paper attempts to determine the capabilities of existing Redundancy Addition and Removal (SRAR) techniques for logic optimization of sequential circuits. To this purpose, we ...
Enrique San Millán, Luis Entrena, Jos&eacut...
ICCAD
2001
IEEE
201views Hardware» more  ICCAD 2001»
14 years 9 months ago
An Integrated Data Path Optimization for Low Power Based on Network Flow Method
Abstract: We propose an effective algorithm for power optimization in behavioral synthesis. In previous work, it has been shown that several hardware allocation/binding problems fo...
Chun-Gi Lyuh, Taewhan Kim, Chien-Liang Liu
ICCAD
2001
IEEE
272views Hardware» more  ICCAD 2001»
14 years 9 months ago
NetBench: A Benchmarking Suite for Network Processors
— In this study we introduce NetBench, a benchmarking suite for network processors. NetBench contains a total of 9 applications that are representative of commercial applications...
Gokhan Memik, William H. Mangione-Smith, Wendong H...