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ICCAD
2008
IEEE
170views Hardware» more  ICCAD 2008»
14 years 9 months ago
Obstacle-avoiding rectilinear Steiner tree construction
— In today’s VLSI designs, there can be many blockages in a routing region. The obstacle-avoiding rectilinear Steiner minimum tree (OARSMT) problem has become an important prob...
Liang Li, Evangeline F. Y. Young
ICCAD
2008
IEEE
151views Hardware» more  ICCAD 2008»
14 years 9 months ago
Race analysis for SystemC using model checking
—SystemC is a system-level modeling language that offers a wide range of features to describe concurrent systems rent levels of abstraction. The SystemC standard permits simulato...
Nicolas Blanc, Daniel Kroening
ICCAD
2008
IEEE
140views Hardware» more  ICCAD 2008»
14 years 9 months ago
To SAT or not to SAT: Ashenhurst decomposition in a large scale
Functional decomposition is a fundamental operation in logic synthesis. Prior BDD-based approaches to functional decomposition suffer from the memory explosion problem and do not...
Hsuan-Po Lin, Jie-Hong Roland Jiang, Ruei-Rung Lee
ICCAD
2008
IEEE
138views Hardware» more  ICCAD 2008»
14 years 9 months ago
Fault tolerant placement and defect reconfiguration for nano-FPGAs
—When manufacturing nano-devices, defects are a certainty and reliability becomes a critical issue. Until now, the most pervasive methods used to address reliability, involve inj...
Amit Agarwal, Jason Cong, Brian Tagiku
ICCAD
2008
IEEE
98views Hardware» more  ICCAD 2008»
14 years 9 months ago
Statistical path selection for at-speed test
Abstract— Process variations make at-speed testing significantly more difficult. They cause subtle delay changes that are distributed rather than the localized nature of a trad...
Vladimir Zolotov, Jinjun Xiong, Hanif Fatemi, Chan...
ICCAD
2008
IEEE
223views Hardware» more  ICCAD 2008»
14 years 9 months ago
Decoupling capacitance allocation for timing with statistical noise model and timing analysis
Abstract— This paper presents an allocation method of decoupling capacitance that explicitly considers timing. We have found and focused that decap does not necessarily improve a...
Takashi Enami, Masanori Hashimoto, Takashi Sato
ICCAD
2008
IEEE
125views Hardware» more  ICCAD 2008»
14 years 9 months ago
A succinct memory model for automated design debugging
— In today’s complex SoC designs, verification and debugging are becoming ever more crucial and increasingly timeconsuming tasks. The prevalence of embedded memories adds to t...
Brian Keng, Hratch Mangassarian, Andreas G. Veneri...
ICCAD
2008
IEEE
103views Hardware» more  ICCAD 2008»
14 years 9 months ago
Pyramids: an efficient computational geometry-based approach for timing-driven placement
Tao Luo, David A. Papa, Zhuo Li, Chin-Ngai Sze, Ch...
ICCAD
2008
IEEE
177views Hardware» more  ICCAD 2008»
14 years 9 months ago
Double patterning technology friendly detailed routing
— Double patterning technology (DPT) is a most likely lithography solution for 32/22nm technology nodes as of 2008 due to the delay of Extreme Ultra Violet lithography. However, ...
Minsik Cho, Yongchan Ban, David Z. Pan
ICCAD
2008
IEEE
87views Hardware» more  ICCAD 2008»
14 years 9 months ago
Routing for chip-package-board co-design considering differential pairs
Jia-Wei Fang, Kuan-Hsien Ho, Yao-Wen Chang