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ICCAD
2008
IEEE
115views Hardware» more  ICCAD 2008»
14 years 7 months ago
Minimizing the energy cost of throughput in a linear pipeline by opportunistic time borrowing
- In this paper, we present a technique to optimize the energy-delay product of a synchronous linear pipeline circuit with dynamic error detection and correction capability running...
Mohammad Ghasemazar, Massoud Pedram
ICCAD
2008
IEEE
127views Hardware» more  ICCAD 2008»
14 years 7 months ago
System-level power estimation using an on-chip bus performance monitoring unit
In this paper we propose an on-chip bus PMU which makes accurate estimates of system power consumption from a first-order linear power model by utilizing system-level activity in...
Youngjin Cho, Younghyun Kim, Sangyoung Park, Naehy...
ICCAD
2008
IEEE
103views Hardware» more  ICCAD 2008»
14 years 7 months ago
On capture power-aware test data compression for scan-based testing
Large test data volume and high test power are two of the major concerns for the industry when testing large integrated circuits. With given test cubes in scan-based testing, the ...
Jia Li, Xiao Liu, Yubin Zhang, Yu Hu, Xiaowei Li, ...
ICCAD
2008
IEEE
153views Hardware» more  ICCAD 2008»
14 years 7 months ago
Boolean factoring and decomposition of logic networks
This paper presents new methods for restructuring logic networks based on fast Boolean techniques. The basis for these are 1) a cut based view of a logic network, 2) exploiting th...
Alan Mishchenko, Robert K. Brayton, Satrajit Chatt...
ICCAD
2008
IEEE
127views Hardware» more  ICCAD 2008»
14 years 7 months ago
Verification of arithmetic datapaths using polynomial function models and congruence solving
Abstract— This paper addresses the problem of solving finite word-length (bit-vector) arithmetic with applications to equivalence verification of arithmetic datapaths. Arithmet...
Neal Tew, Priyank Kalla, Namrata Shekhar, Sivaram ...
ICCAD
2008
IEEE
140views Hardware» more  ICCAD 2008»
14 years 7 months ago
Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure
We propose a post-placement physical synthesis algorithm that can apply multiple circuit synthesis and placement transforms on a placed circuit to improve the critical path delay ...
Huan Ren, Shantanu Dutt
ICCAD
2008
IEEE
147views Hardware» more  ICCAD 2008»
14 years 7 months ago
Overlay aware interconnect and timing variation modeling for double patterning technology
— As Double Patterning Technology (DPT) becomes the only solution for 32-nm lithography process, we need to investigate how DPT affects the performance of a chip. In this paper, ...
Jae-Seok Yang, David Z. Pan
ICCAD
2008
IEEE
246views Hardware» more  ICCAD 2008»
14 years 7 months ago
Integrated circuit design with NEM relays
—To overcome the energy-efficiency limitations imposed by finite sub-threshold slope in CMOS transistors, this paper explores the design of integrated circuits based on nanoelect...
Fred Chen, Hei Kam, Dejan Markovic, Tsu-Jae King L...
ICCAD
2008
IEEE
97views Hardware» more  ICCAD 2008»
14 years 7 months ago
Integrated code and data placement in two-dimensional mesh based chip multiprocessors
— As transistor sizes continue to shrink and the number of transistors per chip keeps increasing, chip multiprocessors (CMPs) are becoming a promising alternative to remain on th...
Taylan Yemliha, Shekhar Srikantaiah, Mahmut T. Kan...