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ICCD
2007
IEEE
105views Hardware» more  ICCD 2007»
14 years 7 months ago
Exploring the interplay of yield, area, and performance in processor caches
The deployment of future deep submicron technology calls for a careful review of existing cache organizations and design practices in terms of yield and performance. This paper pr...
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
ICCD
2007
IEEE
132views Hardware» more  ICCD 2007»
14 years 7 months ago
A position-insensitive finished store buffer
This paper presents the Finished Store Buffer (or FSB), an alternative and position-insensitive approach for building a scalable store buffer for an out-of-order processor. Exploi...
Erika Gunadi, Mikko H. Lipasti