Exploring the interplay of yield, area, and performance in processor caches

The deployment of future deep submicron technology calls for a careful review of existing cache organizations and design practices in terms of yield and performance. This paper presents a cache design flow that enables processor architects to consider yield, area, and performance (YAP) together in a unified framework. Since there is a complex, changing trade-off between these metrics depending on the technology, the cache organization, and the yield enhancement scheme employed, such a design flow becomes invaluable to processor architects when they assess a design and explore the design space quickly at an early stage. We develop a complete set of tools supporting the proposed design flow, from injecting defects into a wafer to evaluating program performance of individual processors in the wafer. A case study is presented to demonstrate the effectiveness of the proposed design flow and developed tools.

• Type: Conference
• Year: 2007
• Where: ICCD
• Authors: Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
• Keywords: Cache Design, Enables Processor Architects, Hardware, ICCD 2007, Yield Enhancement Scheme