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ICCD
2008
IEEE
117views Hardware» more  ICCD 2008»
14 years 9 months ago
RMA: A Read Miss-Based Spin-Down Algorithm using an NV cache
—It is an important issue to reduce the power consumption of a hard disk that takes a large amount of computer system’s power. As a new trend, an NV cache is used to make a dis...
Hyotaek Shim, Jaegeuk Kim, Dawoon Jung, Jin-Soo Ki...
ICCD
2008
IEEE
115views Hardware» more  ICCD 2008»
14 years 9 months ago
Techniques for increasing effective data bandwidth
—In this paper we examine techniques for increasing the effective bandwidth of the microprocessor offchip interconnect. We focus on mechanisms that are orthogonal to other techni...
Christopher Nitta, Matthew Farrens
ICCD
2008
IEEE
165views Hardware» more  ICCD 2008»
14 years 9 months ago
Analysis and minimization of practical energy in 45nm subthreshold logic circuits
Abstract— Over the last decade, the design of ultra-lowpower digital circuits in subthreshold regime has been driven by the quest for minimum energy per operation. In this contri...
David Bol, Renaud Ambroise, Denis Flandre, Jean-Di...
ICCD
2008
IEEE
163views Hardware» more  ICCD 2008»
14 years 9 months ago
Low-cost open-page prefetch scheduling in chip multiprocessors
Marius Grannæs, Magnus Jahre, Lasse Natvig
ICCD
2008
IEEE
159views Hardware» more  ICCD 2008»
14 years 9 months ago
Optimizing data sharing and address translation for the Cell BE Heterogeneous Chip Multiprocessor
— Heterogeneous Chip Multiprocessors (HMPs), such as the Cell Broadband Engine, offer a new design optimization opportunity by allowing designers to provide accelerators for appl...
Michael Gschwind
ICCD
2008
IEEE
146views Hardware» more  ICCD 2008»
14 years 9 months ago
Chip level thermal profile estimation using on-chip temperature sensors
—This paper addresses the problem of chip level thermal profile estimation using runtime temperature sensor readings. We address the challenges of a) availability of only a few t...
Yufu Zhang, Ankur Srivastava, Mohamed M. Zahran
ICCD
2008
IEEE
111views Hardware» more  ICCD 2008»
14 years 9 months ago
Test-access mechanism optimization for core-based three-dimensional SOCs
— Test-access mechanisms (TAMs) and test wrappers (e.g., the IEEE Standard 1500 wrapper) facilitate the modular testing of embedded cores in a core-based system-on-chip (SOC). Su...
Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yua...
ICCD
2008
IEEE
420views Hardware» more  ICCD 2008»
14 years 9 months ago
Frequency and voltage planning for multi-core processors under thermal constraints
— Clock frequency and transistor density increases have resulted in elevated chip temperatures. In order to meet temperature constraints while still exploiting the performance op...
Michael Kadin, Sherief Reda
ICCD
2008
IEEE
117views Hardware» more  ICCD 2008»
14 years 9 months ago
Two dimensional highly associative level-two cache design
High associativity is important for level-two cache designs [9]. Implementing CAM-based Highly Associative Caches (CAM-HAC), however, is both costly in hardware and exhibits poor s...
Chuanjun Zhang, Bing Xue
ICCD
2008
IEEE
139views Hardware» more  ICCD 2008»
14 years 9 months ago
Probabilistic error propagation in logic circuits using the Boolean difference calculus
- A gate level probabilistic error propagation model is presented which takes as input the Boolean function of the gate, the signal and error probabilities of the gate inputs, and ...
Nasir Mohyuddin, Ehsan Pakbaznia, Massoud Pedram