To support dynamic address translation in today's microprocessors, the first-level cache is accessed in parallel with a translation lookaside buffer (TLB). However, this curre...
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
A high performance architecture of elliptic curve scalar multiplication over finite field GF(2m ) is proposed. A pseudo-pipelined word serial finite field multiplier with word siz...
Abstract--Testing security systems is challenging because a system's authors have to play the double role of attackers and defenders. Red Team/Blue Team exercises are an inval...
Jelena Mirkovic, Peter L. Reiher, Christos Papadop...
Abstract-- Preventing silicon chips from negative, even disastrous thermal hazards has become increasingly challenging these days; considering thermal effects early in the design c...
Wei Huang, Karthik Sankaranarayanan, Kevin Skadron...
Synchronous systems offer clean semantics and an easy verification path at the expense of often inefficient implementations. Capturing design specifications as synchronous models a...
Stavros Tripakis, Claudio Pinello, Albert Benvenis...
Multimedia applications usually have throughput constraints. An implementation must meet these constraints, while it minimizes resource usage and energy consumption. The compute in...
In this paper, the problem of finding good wordlength combinations for fixed-point digital signal processing flowgraphs is addressed. By formulating and solving an approximate opti...
This paper examines the hardware implementation trade-offs when evaluating functions via piecewise polynomial approximations and interpolations for precisions of up to 24 bits. In ...
Dong-U Lee, Ray C. C. Cheung, Wayne Luk, John D. V...