Sciweavers

ASPDAC
2012
ACM
279views Hardware» more  ASPDAC 2012»
12 years 6 months ago
Block-level 3D IC design with through-silicon-via planning
— Since re-designing and re-optimizing existing logic, memory, and IP blocks in a 3D fashion significantly increases design cost, nearterm three-dimensional integrated circuit (...
Dae Hyun Kim, Rasit Onur Topaloglu, Sung Kyu Lim
COMBINATORICS
2006
147views more  COMBINATORICS 2006»
13 years 11 months ago
Domino Fibonacci Tableaux
In 2001, Shimozono and White gave a description of the domino Schensted algorithm of Barbasch, Vogan, Garfinkle and van Leeuwen with the "color-to-spin" property, that i...
Naiomi Cameron, Kendra Killpatrick
DATE
2006
IEEE
114views Hardware» more  DATE 2006»
14 years 5 months ago
3D floorplanning with thermal vias
Abstract— 3D circuits have the potential to improve performance over traditional 2D circuits by reducing wirelength and interconnect delay. One major problem with 3D circuits is ...
Eric Wong, Sung Kyu Lim
DAC
2006
ACM
14 years 12 months ago
Novel full-chip gridless routing considering double-via insertion
As the technology node advances into the nanometer era, via-open defects are one of the dominant failures. To improve via yield and reliability, redundant-via insertion is a highl...
Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lum...