This paper explores hardware-implemented error-detection and security mechanisms embedded as modules in a hardware-level framework called the Reliability and Security Engine (RSE)...
Nithin Nakka, Zbigniew Kalbarczyk, Ravishankar K. ...
We show how to automatically verify that complex XScale-like pipelined machine models satisfy the same safety and liveness properties as their corresponding instruction set archit...
This paper explores a novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications. Throu...
Traditional compilers perform their code generation tasks based on a fixed, pre-determined instruction set. This paper describes the implementation of a compiler that determines ...
Abstract. Information hiding has been studied in many security applications such as authentication, copyright management and digital forensics. In this work, we introduce a new app...
Ashwin Swaminathan, Yinian Mao, Min Wu, Krishnan K...
We present a tool which is designed to be used as a code compression advisory system for object code to be run on an embedded processor. All the compression schemes support run-ti...
Current microprocessor instruction set architectures are word oriented, with some subword support. Many important applications, however, can realize substantial performance benefi...
Current Application Specific Instruction set Processor (ASIP) design methodologies are mostly based on iterative architecture exploration that uses Architecture Description Langua...
Kingshuk Karuri, Mohammad Abdullah Al Faruque, Ste...
New application-focused system-on-chip platforms motivate new application-specific processors. Configurable and extensible processor architectures offer the efficiency of tuned lo...
Albert Wang, Earl Killian, Dror E. Maydan, Chris R...