Fault Tolerant System Design Method Based on Self-Checking Circuits

This paper describes a highly reliable digital circuit design method based on totally self checking blocks implemented in FPGAs. The bases of the self checking blocks are parity predictors. The parity predictor design method based on multiple parity groups is proposed. Proper parity groups are chosen in order to obtain minimal area overhead and to decrease the number of undetectable faults.

• Type: Conference
• Year: 2006
• Where: IOLTS
• Authors: Pavel Kubalík, Petr Fiser, Hana Kubatova
• Keywords: IOLTS 2006, Parity Groups, Parity Predictor, Self Checking Blocks, Software Engineering