ISCA
1998
IEEE
14 years 3 months ago
1998
IEEE
Control-flow misprediction penalties are a major impediment to high performance in wide-issue superscalar processors. In this paper we present Selective Eager Execution (SEE), an ...
ISCA
1998
IEEE
14 years 3 months ago
1998
IEEE
Commercial applications are an important, yet often overlooked, workload with significantly different characteristics from technical workloads. The potential impact of these diffe...
ISCA
1998
IEEE
14 years 3 months ago
1998
IEEE
Much of the improvement in computer performance over the last twenty years has come from faster transistors and architectural advances that increase parallelism. Historically, par...
ISCA
1998
IEEE
14 years 3 months ago
1998
IEEE
Accurate branch prediction is essential for obtaining high performance in pipelined superscalar processors that execute instructions speculatively. Some of the best current predic...
ISCA
1998
IEEE
14 years 3 months ago
1998
IEEE
Modern processors improve instruction level parallelism by speculation. The outcome of data and control decisions is predicted, and the operations are speculatively executed and o...
ISCA
1998
IEEE
14 years 3 months ago
1998
IEEE
Pipeline flushes due to branch mispredictions is one of the most serious problems facing the designer of a deeply pipelined, superscalar processor. Many branch predictors have bee...
ISCA
1998
IEEE
14 years 3 months ago
1998
IEEE
The design challenge for large-scale multiprocessors is (1) to minimize communication overhead, (2) allow communication to overlap computation, and (3) coordinate the two without ...
ISCA
1998
IEEE
14 years 3 months ago
1998
IEEE
Computer systems have become powerful enough to process continuous data streams such as video or animated graphics. While processing power and communication bandwidth of today...
ISCA
1998
IEEE
14 years 3 months ago
1998
IEEE
Indirect branch prediction is likely to become increasingly important in the future because indirect branches occur more frequently in object-oriented programs. With misprediction ...
ISCA
1998
IEEE
14 years 3 months ago
1998
IEEE
For maximum performance, an out-of-order processor must issue load instructions as early as possible, while avoiding memory-order violations with prior store instructions that wri...