ISCA
2003
IEEE
14 years 6 months ago
2003
IEEE
Designing ASICs for each new generation of backbone routers is a time intensive and fiscally draining process. In this paper we focus on the design of a programmable architecture...
ISCA
2003
IEEE
14 years 6 months ago
2003
IEEE
In a single second a modern processor can execute billions of instructions. Obtaining a bird’s eye view of the behavior of a program at these speeds can be a difficult task whe...
ISCA
2003
IEEE
14 years 6 months ago
2003
IEEE
While removing software bugs consumes vast amounts of human time, hardware support for debugging in modern computers remains rudimentary. Fortunately, we show that mechanisms for ...
ISCA
2003
IEEE
14 years 6 months ago
2003
IEEE
Scaling of CMOS technology causes the power supply voltages to fall and supply currents to rise at the same time as operating speeds are increasing. Falling supply voltages cause ...
ISCA
2003
IEEE
14 years 6 months ago
2003
IEEE
This paper describes the polymorphous TRIPS architecture which can be configured for different granularities and types of parallelism. TRIPS contains mechanisms that enable the p...
ISCA
2003
IEEE
14 years 6 months ago
2003
IEEE
As quantum computing moves closer to reality the need for basic architectural studies becomes more pressing. Quantum wires, which transport quantum data, will be a fundamental com...
ISCA
2003
IEEE
14 years 6 months ago
2003
IEEE
As processor back-ends get more aggressive, front-ends will have to scale as well. Although the back-ends of superscalar processors have continued to become more parallel, the fro...
ISCA
2003
IEEE
14 years 6 months ago
2003
IEEE
Many future shared-memory multiprocessor servers will both target commercial workloads and use highly-integrated “glueless” designs. Implementing low-latency cache coherence i...
ISCA
2003
IEEE
14 years 6 months ago
2003
IEEE
Despite their superior performance for multimedia applications, vector processors have three limitations that hinder their widespread acceptance. First, the complexity and size of...
ISCA
2003
IEEE
14 years 6 months ago
2003
IEEE
Current-generation microprocessors are designed to process instructions with one and two source operands at equal cost. Handling two source operands requires multiple ports for ea...