ISCA
2006
IEEE
14 years 6 months ago
2006
IEEE
ISCA
2006
IEEE
14 years 6 months ago
2006
IEEE
ISCA
2006
IEEE
14 years 6 months ago
2006
IEEE
Microprocessor design is undergoing a major paradigm shift towards multi-core designs, in anticipation that future performance gains will come from exploiting threadlevel parallel...
ISCA
2006
IEEE
14 years 6 months ago
2006
IEEE
ISCA
2006
IEEE
14 years 6 months ago
2006
IEEE
Improvements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future...
ISCA
2006
IEEE
14 years 6 months ago
2006
IEEE
This paper presents CMP Cooperative Caching, a unified framework to manage a CMP’s aggregate on-chip cache resources. Cooperative caching combines the strengths of private and ...
ISCA
2006
IEEE
14 years 6 months ago
2006
IEEE
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
ISCA
2006
IEEE
14 years 6 months ago
2006
IEEE
Thread-level speculation (TLS) has proven to be a promising method of extracting parallelism from both integer and scientific workloads, targeting speculative threads that range ...
ISCA
2006
IEEE
14 years 6 months ago
2006
IEEE
The key to high performance in Simultaneous Multithreaded (SMT) processors lies in optimizing the distribution of shared resources to active threads. Existing resource distributio...
ISCA
2006
IEEE
14 years 6 months ago
2006
IEEE
We present a novel framework for defining memory models in terms of two properties: thread-local Instruction Reordering axioms and Store Atomicity, which describes inter-thread c...